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| author | Theofilos Augoustis <theofilos.augoustis@gmail.com> | 2023-12-14 17:03:59 +0100 |
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| committer | Theofilos Augoustis <theofilos.augoustis@gmail.com> | 2023-12-14 17:03:59 +0100 |
| commit | 194f3d6f2ebdc7b0631fdaaeb8451142b052ccb0 (patch) | |
| tree | 20806871433db331bdfed66ddadfadecbea2b7c4 /arch/x86.py | |
| parent | 4a5584d8f69d8ff511285387971d8cbf803f16b7 (diff) | |
| download | focaccia-194f3d6f2ebdc7b0631fdaaeb8451142b052ccb0.tar.gz focaccia-194f3d6f2ebdc7b0631fdaaeb8451142b052ccb0.zip | |
Implement symbolic comparison and match traces via Miasm
Co-authored-by: Theofilos Augoustis <theofilos.augoustis@gmail.com> Co-authored-by: Nicola Crivellin <nicola.crivellin98@gmail.com>
Diffstat (limited to 'arch/x86.py')
| -rw-r--r-- | arch/x86.py | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/arch/x86.py b/arch/x86.py index 776291d..95e1a82 100644 --- a/arch/x86.py +++ b/arch/x86.py @@ -1,8 +1,10 @@ -"""Architexture-specific configuration.""" +"""Architecture-specific configuration.""" from .arch import Arch -# Names of registers in the architexture +archname = 'x86_64' + +# Names of registers in the architecture regnames = [ 'RIP', 'RAX', @@ -22,11 +24,22 @@ regnames = [ 'R14', 'R15', 'RFLAGS', + + # x87 float registers + 'ST0', 'ST1', 'ST2', 'ST3', 'ST4', 'ST5', 'ST6', 'ST7', + + # Vector registers + 'YMM0', 'YMM1', 'YMM2', 'YMM3', 'YMM4', + 'YMM5', 'YMM6', 'YMM7', 'YMM8', 'YMM9', + 'YMM10', 'YMM11', 'YMM12', 'YMM13', 'YMM14', 'YMM15', + # Segment registers 'CS', 'DS', 'SS', 'ES', 'FS', 'GS', 'FS_BASE', 'GS_BASE', + # FLAGS 'CF', 'PF', 'AF', 'ZF', 'SF', 'TF', 'IF', 'DF', 'OF', 'IOPL', 'NT', + # EFLAGS 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID', ] @@ -74,7 +87,7 @@ def decompose_rflags(rflags: int) -> dict[str, int]: class ArchX86(Arch): def __init__(self): - super().__init__("X86", regnames) + super().__init__(archname, regnames) def to_regname(self, name: str) -> str | None: """The X86 override of the standard register name lookup. |