diff options
| author | Theofilos Augoustis <theofilos.augoustis@gmail.com> | 2025-09-29 10:39:40 +0000 |
|---|---|---|
| committer | Theofilos Augoustis <theofilos.augoustis@gmail.com> | 2025-09-29 10:39:40 +0000 |
| commit | 25e44d6ddf290db968db381b12d59b8b690b1721 (patch) | |
| tree | 11ff01eb8b6ac67fc825dd81af2b0b95337a75be /src/focaccia/lldb_target.py | |
| parent | cbf212bbb4ce51c09326bed44b462529f147820a (diff) | |
| download | focaccia-25e44d6ddf290db968db381b12d59b8b690b1721.tar.gz focaccia-25e44d6ddf290db968db381b12d59b8b690b1721.zip | |
Add basic reproducer for issue 2248 with Focaccia (hacked, does not work yet)
Diffstat (limited to 'src/focaccia/lldb_target.py')
| -rw-r--r-- | src/focaccia/lldb_target.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/focaccia/lldb_target.py b/src/focaccia/lldb_target.py index 1f31337..a6f61bb 100644 --- a/src/focaccia/lldb_target.py +++ b/src/focaccia/lldb_target.py @@ -187,6 +187,8 @@ class LLDBConcreteTarget: the register's value. """ try: + if 'Q' in regname: + regname = 'V' + regname[1:] reg = self._get_register(regname) assert(reg.IsValid()) if reg.size > 8: # reg is a vector register |