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authorReimersS <sebastian.reimers@tum.de>2025-12-01 08:09:18 +0000
committerReimersS <sebastian.reimers@tum.de>2025-12-01 08:09:18 +0000
commite71fe7d045888e8a8fda700cd3e7452b5bade7b6 (patch)
tree611166e3a0527a6db9c0a15c7383e79b0bce2659 /src
parent3e1bb565abc3de8967f0edb7f51ae3667a39c65e (diff)
downloadfocaccia-e71fe7d045888e8a8fda700cd3e7452b5bade7b6.tar.gz
focaccia-e71fe7d045888e8a8fda700cd3e7452b5bade7b6.zip
Fix lldb pc access sr/benchmark-testing
Diffstat (limited to 'src')
-rw-r--r--src/focaccia/native/lldb_target.py5
-rw-r--r--src/focaccia/native/tracer.py6
2 files changed, 7 insertions, 4 deletions
diff --git a/src/focaccia/native/lldb_target.py b/src/focaccia/native/lldb_target.py
index ff43643..177ac21 100644
--- a/src/focaccia/native/lldb_target.py
+++ b/src/focaccia/native/lldb_target.py
@@ -125,7 +125,7 @@ class LLDBConcreteTarget:
             self.run()
             if self.is_exited():
                 return
-            if self.read_register('pc') == address:
+            if self.read_register(self.arch.to_regname('pc')) == address:
                 break
         self.target.BreakpointDelete(bp.GetID())
 
@@ -207,6 +207,9 @@ class LLDBConcreteTarget:
                                       or the target is otherwise unable to read
                                       the register's value.
         """
+        if regname.upper() == self.arch.to_regname('pc'):
+            frame = self.process.GetSelectedThread().GetFrameAtIndex(0)
+            return frame.GetPC()
         try:
             reg = self._get_register(regname)
             assert(reg.IsValid())
diff --git a/src/focaccia/native/tracer.py b/src/focaccia/native/tracer.py
index af53c89..0bca906 100644
--- a/src/focaccia/native/tracer.py
+++ b/src/focaccia/native/tracer.py
@@ -46,7 +46,7 @@ class SpeculativeTracer(ReadableProgramState):
     def __init__(self, target: LLDBConcreteTarget):
         super().__init__(target.arch)
         self.target = target
-        self.pc = target.read_register('pc')
+        self.pc = target.read_register(target.arch.to_regname('pc'))
         self.speculative_pc: int | None = None
         self.speculative_count: int = 0
         
@@ -57,7 +57,7 @@ class SpeculativeTracer(ReadableProgramState):
         if new_pc is None:
             self.progress_execution()
             self.target.step()
-            self.pc = self.target.read_register('pc')
+            self.pc = self.target.read_register(target.arch.to_regname('pc'))
             self.speculative_pc = None
             self.speculative_count = 0
             return
@@ -91,7 +91,7 @@ class SpeculativeTracer(ReadableProgramState):
         if self.target.is_exited():
             return
         self.target.step()
-        self.pc = self.target.read_register('pc')
+        self.pc = self.target.read_register(self.target.arch.to_regname('pc'))
 
     def _cache(self, name: str, value):
         self.read_cache[name] = value