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| author | Theofilos Augoustis <theofilos.augoustis@gmail.com> | 2025-11-10 17:03:03 +0000 |
|---|---|---|
| committer | Theofilos Augoustis <theofilos.augoustis@gmail.com> | 2025-11-10 17:03:03 +0000 |
| commit | 08afe9decbd6047e06133394c7c408d6f2c092db (patch) | |
| tree | d17e29c46fc490dcc85fdea98707035f6371a05a /src | |
| parent | 0b9f774d356c9cfef186d896e3df0b53bf3b87ec (diff) | |
| download | focaccia-ta/rr-mmaps.tar.gz focaccia-ta/rr-mmaps.zip | |
Add type annotation to parser for memory writes ta/rr-mmaps
Diffstat (limited to 'src')
| -rw-r--r-- | src/focaccia/deterministic.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/focaccia/deterministic.py b/src/focaccia/deterministic.py index 77bdcb0..e7914a3 100644 --- a/src/focaccia/deterministic.py +++ b/src/focaccia/deterministic.py @@ -491,7 +491,7 @@ class DeterministicLog: return regs['pc'], regs raise NotImplementedError(f'Unable to parse registers for architecture {arch}') - def parse_memory_writes(event: Frame, reader: io.RawIOBase): + def parse_memory_writes(event: Frame, reader: io.RawIOBase) -> list[MemoryWrite]: writes = [] for raw_write in event.memWrites: # Skip memory writes with 0 bytes |