Enable correct handling of addresses

4 files changed, 11 insertions, 7 deletions

diff --git a/src/focaccia/deterministic.py b/src/focaccia/deterministic.py
index 58d9fd9..4070504 100644
--- a/src/focaccia/deterministic.py
+++ b/src/focaccia/deterministic.py
@@ -30,7 +30,7 @@ class MemoryWrite:
         self.data = data
 
     def __repr__(self) -> str:
-        return f'{{ tid: {hex(self.tid)}, addr: {hex(self.address)}:{hex(self.address+self.size)}\n' \
+        return f'{{ tid: {self.tid}, addr: {hex(self.address)}:{hex(self.address+self.size)}\n' \
                f'   conservative? {self.is_conservative}, holes: {self.holes}\n' \
                f'   data: {self.data} }}'
 
diff --git a/src/focaccia/native/tracer.py b/src/focaccia/native/tracer.py
index eed5206..af53c89 100644
--- a/src/focaccia/native/tracer.py
+++ b/src/focaccia/native/tracer.py
@@ -33,9 +33,12 @@ def match_event(event: Event, target: ReadableProgramState) -> bool:
         for reg, value in event.registers.items():
             if value == event.pc:
                 continue
-            if target.read_register(reg) != value:
-                print(f'Failed match for {reg}: {hex(value)} != {hex(target.read_register(reg))}')
-                return False
+            try:
+                if target.read_register(reg) != value:
+                    print(f'Failed match for {reg}: {hex(value)} != {hex(target.read_register(reg))}')
+                    return False
+            except Exception as e:
+                warn(f'Unable to read register: {e}')
         return True
     return False
 
diff --git a/src/focaccia/qemu/_qemu_tool.py b/src/focaccia/qemu/_qemu_tool.py
index 5a59e15..c838f2b 100644
--- a/src/focaccia/qemu/_qemu_tool.py
+++ b/src/focaccia/qemu/_qemu_tool.py
@@ -8,6 +8,7 @@ work to do.
 
 import logging
 import traceback
+import pyroaring
 from typing import Iterable, Optional
 
 import focaccia.parser as parser
@@ -164,7 +165,7 @@ def collect_conc_trace(gdb: GDBServerStateIterator, strace: Trace) \
 
     # An online trace matching algorithm.
     info(f'Tracing QEMU between {hex(start_addr)}:{hex(strace.env.stop_address) if strace.env.stop_address else "end"}')
-    traced_address_set = frozenset(strace.addresses)
+    traced_address_set = pyroaring.BitMap64(strace.addresses)
 
     transform: Optional[SymbolicTransform] = None
     while True:
diff --git a/src/focaccia/qemu/target.py b/src/focaccia/qemu/target.py
index 28fe805..790249c 100644
--- a/src/focaccia/qemu/target.py
+++ b/src/focaccia/qemu/target.py
@@ -260,7 +260,7 @@ class GDBServerStateIterator(GDBServerConnector):
         self._thread_context = {
         }
         info(f'Synchronized at PC={hex(first_state.read_pc())} to event:\n{event}')
-        debug(f'Thread mapping at this point: {hex(event.tid)}: {hex(self.current_tid())}')
+        debug(f'Thread mapping at this point: {event.tid}: {self.current_tid()}')
 
     def _handle_syscall(self, event: Event, post_event: Event) -> ReadableProgramState:
         call = event.registers.get(self.arch.get_syscall_reg())
@@ -308,7 +308,7 @@ class GDBServerStateIterator(GDBServerConnector):
                 info(f'New thread created TID={hex(new_tid)} corresponds to native {hex(event_new_tid)}')
                 debug('Thread mapping at this point:')
                 for event_tid, (tid, _) in self._thread_map.items():
-                    debug(f'{hex(event_tid)}: {hex(tid)}')
+                    debug(f'{event_tid}: {tid}')
 
             next_state = GDBProgramState(self._process, gdb.selected_frame(), self.arch)