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| author | Theofilos Augoustis <theofilos.augoustis@gmail.com> | 2025-09-29 10:39:40 +0000 |
|---|---|---|
| committer | Theofilos Augoustis <theofilos.augoustis@gmail.com> | 2025-09-29 10:39:40 +0000 |
| commit | 25e44d6ddf290db968db381b12d59b8b690b1721 (patch) | |
| tree | 11ff01eb8b6ac67fc825dd81af2b0b95337a75be /src | |
| parent | cbf212bbb4ce51c09326bed44b462529f147820a (diff) | |
| download | focaccia-25e44d6ddf290db968db381b12d59b8b690b1721.tar.gz focaccia-25e44d6ddf290db968db381b12d59b8b690b1721.zip | |
Add basic reproducer for issue 2248 with Focaccia (hacked, does not work yet)
Diffstat (limited to 'src')
| -rw-r--r-- | src/focaccia/lldb_target.py | 2 | ||||
| -rw-r--r-- | src/focaccia/symbolic.py | 6 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/focaccia/lldb_target.py b/src/focaccia/lldb_target.py index 1f31337..a6f61bb 100644 --- a/src/focaccia/lldb_target.py +++ b/src/focaccia/lldb_target.py @@ -187,6 +187,8 @@ class LLDBConcreteTarget: the register's value. """ try: + if 'Q' in regname: + regname = 'V' + regname[1:] reg = self._get_register(regname) assert(reg.IsValid()) if reg.size > 8: # reg is a vector register diff --git a/src/focaccia/symbolic.py b/src/focaccia/symbolic.py index 9aeff56..444145f 100644 --- a/src/focaccia/symbolic.py +++ b/src/focaccia/symbolic.py @@ -594,10 +594,14 @@ class _LLDBConcreteState(ReadableProgramState): def read_register(self, reg: str) -> int: regname = self.arch.to_regname(reg) - if regname is None: + if regname is None and reg != "DCZID_EL0" and reg != "TPIDR_EL0": raise RegisterAccessError(reg, f'Not a register name: {reg}') try: + if reg == "DCZID_EL0": + return 4 + if reg == "TPIDR_EL0": + return 0x4206c8 return self._target.read_register(regname) except ConcreteRegisterError: raise RegisterAccessError(regname, '') |