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| author | Theofilos Augoustis <theofilos.augoustis@tum.de> | 2025-08-27 15:44:57 +0000 |
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| committer | Theofilos Augoustis <theofilos.augoustis@tum.de> | 2025-08-27 16:46:29 +0000 |
| commit | 9729ae38f8e44a17cb0915952791b5b906b4b7fa (patch) | |
| tree | e2e0dd02d4eae136e7475346ab4f09c18930876e /test/test_snapshot.py | |
| parent | 849e5a6ec6e0246b5dde1fb2583aa13ed288e9c1 (diff) | |
| download | focaccia-9729ae38f8e44a17cb0915952791b5b906b4b7fa.tar.gz focaccia-9729ae38f8e44a17cb0915952791b5b906b4b7fa.zip | |
Migrate to nix flakes, uv and pyproject toml for builds
Diffstat (limited to 'test/test_snapshot.py')
| -rw-r--r-- | test/test_snapshot.py | 74 |
1 files changed, 0 insertions, 74 deletions
diff --git a/test/test_snapshot.py b/test/test_snapshot.py deleted file mode 100644 index ddad410..0000000 --- a/test/test_snapshot.py +++ /dev/null @@ -1,74 +0,0 @@ -import unittest - -from focaccia.arch import x86 -from focaccia.snapshot import ProgramState, RegisterAccessError - -class TestProgramState(unittest.TestCase): - def setUp(self): - self.arch = x86.ArchX86() - - def test_register_access_empty_state(self): - state = ProgramState(self.arch) - for reg in x86.regnames: - self.assertRaises(RegisterAccessError, state.read_register, reg) - - def test_register_read_write(self): - state = ProgramState(self.arch) - for reg in x86.regnames: - state.set_register(reg, 0x42) - for reg in x86.regnames: - val = state.read_register(reg) - self.assertEqual(val, 0x42) - - def test_register_aliases_empty_state(self): - state = ProgramState(self.arch) - for reg in self.arch.all_regnames: - self.assertRaises(RegisterAccessError, state.read_register, reg) - - def test_register_aliases_read_write(self): - state = ProgramState(self.arch) - for reg in ['EAX', 'EBX', 'ECX', 'EDX']: - state.set_register(reg, 0xa0ff0) - - for reg in ['AH', 'BH', 'CH', 'DH']: - self.assertEqual(state.read_register(reg), 0xf, reg) - for reg in ['AL', 'BL', 'CL', 'DL']: - self.assertEqual(state.read_register(reg), 0xf0, reg) - for reg in ['AX', 'BX', 'CX', 'DX']: - self.assertEqual(state.read_register(reg), 0x0ff0, reg) - for reg in ['EAX', 'EBX', 'ECX', 'EDX', - 'RAX', 'RBX', 'RCX', 'RDX']: - self.assertEqual(state.read_register(reg), 0xa0ff0, reg) - - def test_flag_aliases(self): - flags = ['CF', 'PF', 'AF', 'ZF', 'SF', 'TF', 'IF', 'DF', 'OF', - 'IOPL', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'] - state = ProgramState(self.arch) - - state.set_register('RFLAGS', 0) - for flag in flags: - self.assertEqual(state.read_register(flag), 0) - - state.set_register('RFLAGS', - x86.compose_rflags({'ZF': 1, 'PF': 1, 'OF': 0})) - self.assertEqual(state.read_register('ZF'), 1, self.arch.get_reg_accessor('ZF')) - self.assertEqual(state.read_register('PF'), 1) - self.assertEqual(state.read_register('OF'), 0) - self.assertEqual(state.read_register('AF'), 0) - self.assertEqual(state.read_register('ID'), 0) - self.assertEqual(state.read_register('SF'), 0) - - for flag in flags: - state.set_register(flag, 1) - for flag in flags: - self.assertEqual(state.read_register(flag), 1) - - state.set_register('OF', 1) - state.set_register('AF', 1) - state.set_register('SF', 1) - self.assertEqual(state.read_register('OF'), 1) - self.assertEqual(state.read_register('AF'), 1) - self.assertEqual(state.read_register('SF'), 1) - -if __name__ == '__main__': - unittest.main() |