diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/focaccia/lldb_target.py | 2 | ||||
| -rw-r--r-- | src/focaccia/symbolic.py | 6 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/focaccia/lldb_target.py b/src/focaccia/lldb_target.py index 1f31337..a6f61bb 100644 --- a/src/focaccia/lldb_target.py +++ b/src/focaccia/lldb_target.py @@ -187,6 +187,8 @@ class LLDBConcreteTarget: the register's value. """ try: + if 'Q' in regname: + regname = 'V' + regname[1:] reg = self._get_register(regname) assert(reg.IsValid()) if reg.size > 8: # reg is a vector register diff --git a/src/focaccia/symbolic.py b/src/focaccia/symbolic.py index 9aeff56..444145f 100644 --- a/src/focaccia/symbolic.py +++ b/src/focaccia/symbolic.py @@ -594,10 +594,14 @@ class _LLDBConcreteState(ReadableProgramState): def read_register(self, reg: str) -> int: regname = self.arch.to_regname(reg) - if regname is None: + if regname is None and reg != "DCZID_EL0" and reg != "TPIDR_EL0": raise RegisterAccessError(reg, f'Not a register name: {reg}') try: + if reg == "DCZID_EL0": + return 4 + if reg == "TPIDR_EL0": + return 0x4206c8 return self._target.read_register(regname) except ConcreteRegisterError: raise RegisterAccessError(regname, '') |