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| author | Ajax <commial@gmail.com> | 2016-12-22 18:22:19 +0100 |
|---|---|---|
| committer | Ajax <commial@gmail.com> | 2017-01-04 17:14:55 +0100 |
| commit | 0831662234778e438657e89e1af5c4f3515c4135 (patch) | |
| tree | f15453a84830a55ef277c8de90ac18e878d46065 | |
| parent | 424e94a769523f3c3ba4a26ac51e9443fc9e99e3 (diff) | |
| download | miasm-0831662234778e438657e89e1af5c4f3515c4135.tar.gz miasm-0831662234778e438657e89e1af5c4f3515c4135.zip | |
LLVM: Add missing operation BSR/BSF
Diffstat (limited to '')
| -rw-r--r-- | miasm2/jitter/llvmconvert.py | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/miasm2/jitter/llvmconvert.py b/miasm2/jitter/llvmconvert.py index 83ee64a7..44495ad3 100644 --- a/miasm2/jitter/llvmconvert.py +++ b/miasm2/jitter/llvmconvert.py @@ -230,6 +230,12 @@ class LLVMContext_JIT(LLVMContext): itype, itype, itype]}}) + self.add_fc({"x86_bsr": {"ret": itype, + "args": [itype, + itype]}}) + self.add_fc({"x86_bsf": {"ret": itype, + "args": [itype, + itype]}}) self.add_fc({"segm2addr": {"ret": itype, "args": [p8, itype, @@ -333,6 +339,8 @@ class LLVMFunction(): '>>>': 'rot_right', '<<<c_rez': 'rcl_rez_op', '>>>c_rez': 'rcr_rez_op', + 'bsr': 'x86_bsr', + 'bsf': 'x86_bsf', } ## Add the size as suffix op_translate_with_suffix_size = {'bcdadd': 'bcdadd', |