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| author | Zheng Luo <vicluo96@gmail.com> | 2019-10-06 18:36:58 -0700 |
|---|---|---|
| committer | Zheng Luo <vicluo96@gmail.com> | 2019-10-06 18:38:29 -0700 |
| commit | 259914c5d835421e2785d4b6bcff74f1ce5532b3 (patch) | |
| tree | 97511b2913338ea59a07ba598c6b14bfe6aacb57 | |
| parent | 88b714154312948979488e142726fd18680b6220 (diff) | |
| download | miasm-259914c5d835421e2785d4b6bcff74f1ce5532b3.tar.gz miasm-259914c5d835421e2785d4b6bcff74f1ce5532b3.zip | |
arch: x86: make UD2 break control flow
Diffstat (limited to '')
| -rw-r--r-- | miasm/arch/x86/arch.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/miasm/arch/x86/arch.py b/miasm/arch/x86/arch.py index 3053301a..df6fa8b7 100644 --- a/miasm/arch/x86/arch.py +++ b/miasm/arch/x86/arch.py @@ -496,7 +496,7 @@ class instruction_x86(instruction): return True if self.name.startswith('SYS'): return True - return self.name in ['CALL', 'HLT', 'IRET', 'IRETD', 'IRETQ', 'ICEBP'] + return self.name in ['CALL', 'HLT', 'IRET', 'IRETD', 'IRETQ', 'ICEBP', 'UD2'] def splitflow(self): if self.name in conditional_branch: |