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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2020-10-04 23:13:40 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2020-10-04 23:13:40 +0200 |
| commit | 2b9228e6cf4afdfa3ece8b84e5905934d97e5660 (patch) | |
| tree | 2a6b43df48e3f1213f9fe4c1a70b4daaf2b54f15 | |
| parent | 218492cd10b339a8d47d2fdbd61953fcf954fb8b (diff) | |
| download | miasm-2b9228e6cf4afdfa3ece8b84e5905934d97e5660.tar.gz miasm-2b9228e6cf4afdfa3ece8b84e5905934d97e5660.zip | |
Set RAX high bits 0 only in 64bit
Diffstat (limited to '')
| -rw-r--r-- | miasm/arch/x86/sem.py | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/miasm/arch/x86/sem.py b/miasm/arch/x86/sem.py index 6e593f51..da95dd68 100644 --- a/miasm/arch/x86/sem.py +++ b/miasm/arch/x86/sem.py @@ -403,7 +403,13 @@ def gen_cmov(ir, instr, cond, dst, src, mov_if): dstA, dstB = loc_do_expr, loc_skip_expr else: dstA, dstB = loc_skip_expr, loc_do_expr - e = [m2_expr.ExprAssign(dst, dst)] + e = [] + if instr.mode == 64: + # Force destination set in order to zero high bit orders + # In 64 bit: + # cmovz eax, ebx + # if zf == 0 => high part of RAX is set to zero + e = [m2_expr.ExprAssign(dst, dst)] e_do, extra_irs = mov(ir, instr, dst, src) e_do.append(m2_expr.ExprAssign(ir.IRDst, loc_skip_expr)) e.append(m2_expr.ExprAssign(ir.IRDst, m2_expr.ExprCond(cond, dstA, dstB))) |