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| author | woni <81616747+W0ni@users.noreply.github.com> | 2023-09-13 10:34:16 +0200 |
|---|---|---|
| committer | woni <81616747+W0ni@users.noreply.github.com> | 2023-09-13 10:34:16 +0200 |
| commit | 71e4e09da6816a72905adeea3c0864714353c406 (patch) | |
| tree | 33ab1ef18c7004812373184fe7b24758e35ce0c1 | |
| parent | bb53a4505ab43662d5ebb9349ecda93eacaa447c (diff) | |
| download | miasm-71e4e09da6816a72905adeea3c0864714353c406.tar.gz miasm-71e4e09da6816a72905adeea3c0864714353c406.zip | |
Fix disassembly bug
Diffstat (limited to '')
| -rw-r--r-- | miasm/arch/arm/arch.py | 4 | ||||
| -rwxr-xr-x | test/arch/arm/sem.py | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/miasm/arch/arm/arch.py b/miasm/arch/arm/arch.py index 5ccf5eca..91c22bd5 100644 --- a/miasm/arch/arm/arch.py +++ b/miasm/arch/arm/arch.py @@ -1148,8 +1148,12 @@ class arm_op2(arm_arg): shift_op = ExprInt(amount, 32) a = regs_expr[rm] if shift_op == ExprInt(0, 32): + #rrx if shift_type == 3: self.expr = ExprOp(allshifts[4], a) + #asr, lsr + elif shift_type == 1 or shift_type == 2: + self.expr = ExprOp(allshifts[shift_type], a, ExprInt(32, 32)) else: self.expr = a else: diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py index a5b6d5eb..c80b471d 100755 --- a/test/arch/arm/sem.py +++ b/test/arch/arm/sem.py @@ -81,7 +81,7 @@ class TestARMSemantic(unittest.TestCase): self.assertEqual( compute('MOV R4, R4 LSR 31', {R4: 0xDEADBEEF, }), {R4: 0x00000001, }) self.assertEqual( - compute('MOV R4, R4 LSR 32', {R4: 0xDEADBEEF, }), {R4: 0xDEADBEEF, }) + compute('MOV R4, R4 LSR 32', {R4: 0xDEADBEEF, }), {R4: 0x0, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 LSR 33') self.assertEqual( compute('MOV R4, R4 LSR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0x6F56DF77, R5: 0xBADBAD01, }) @@ -93,7 +93,7 @@ class TestARMSemantic(unittest.TestCase): self.assertEqual( compute('MOV R4, R4 ASR 31', {R4: 0xDEADBEEF, }), {R4: 0xFFFFFFFF, }) self.assertEqual( - compute('MOV R4, R4 ASR 32', {R4: 0xDEADBEEF, }), {R4: 0xDEADBEEF, }) + compute('MOV R4, R4 ASR 32', {R4: 0xDEADBEEF, }), {R4: 0xFFFFFFFF, }) self.assertRaises(ValueError, compute, 'MOV R4, R4 ASR 33') self.assertEqual( compute('MOV R4, R4 ASR R5', {R4: 0xDEADBEEF, R5: 0xBADBAD01, }), {R4: 0xEF56DF77, R5: 0xBADBAD01, }) |