New opcodes and little bugfix

3 files changed, 167 insertions, 5 deletions

diff --git a/miasm/arch/mips32/arch.py b/miasm/arch/mips32/arch.py
index dcdfb707..f4a0f0d1 100644
--- a/miasm/arch/mips32/arch.py
+++ b/miasm/arch/mips32/arch.py
@@ -321,6 +321,26 @@ class mips32_s16imm_noarg(mips32_imm):
         self.value = v
         return True
 
+
+class mips32_s09imm_noarg(mips32_imm):
+    def decode(self, v):
+        v = v & self.lmask
+        v = cpu.sign_ext(v, 9, 32)
+        self.expr = ExprInt(v, 32)
+        return True
+
+    def encode(self):
+        if not isinstance(self.expr, ExprInt):
+            return False
+        v = int(self.expr)
+        if v & 0x80000000:
+            nv = v & ((1 << 9) - 1)
+            assert( v == cpu.sign_ext(nv, 9, 32))
+            v = nv
+        self.value = v
+        return True
+
+
 class mips32_soff_noarg(mips32_imm):
     def decode(self, v):
         v = v & self.lmask
@@ -346,6 +366,9 @@ class mips32_soff_noarg(mips32_imm):
 class mips32_s16imm(mips32_s16imm_noarg, mips32_arg):
     pass
 
+class mips32_s09imm(mips32_s09imm_noarg, mips32_arg):
+    pass
+
 class mips32_soff(mips32_soff_noarg, mips32_arg):
     pass
 
@@ -471,16 +494,22 @@ fd = cpu.bs(l=5, cls=(mips32_fltpreg,))
 
 s16imm = cpu.bs(l=16, cls=(mips32_s16imm,))
 u16imm = cpu.bs(l=16, cls=(mips32_u16imm,))
+s09imm = cpu.bs(l=9, cls=(mips32_s09imm,))
 sa = cpu.bs(l=5, cls=(mips32_u16imm,))
 base = cpu.bs(l=5, cls=(mips32_dreg_imm,))
 soff = cpu.bs(l=16, cls=(mips32_soff,))
+oper = cpu.bs(l=5, cls=(mips32_u16imm,))
 
 cpr0 = cpu.bs(l=5, cls=(mips32_imm,), fname="cpr0")
 cpr =  cpu.bs(l=3, cls=(mips32_cpr,))
 
+stype = cpu.bs(l=5, cls=(mips32_u16imm,))
+hint_pref = cpu.bs(l=5, cls=(mips32_u16imm,))
 
 s16imm_noarg = cpu.bs(l=16, cls=(mips32_s16imm_noarg,), fname="imm",
                   order=-1)
+s09imm_noarg = cpu.bs(l=9, cls=(mips32_s09imm_noarg,), fname="imm",
+                  order=-1)
 
 hint = cpu.bs(l=5, default_val="00000")
 fcc = cpu.bs(l=3, cls=(mips32_fccreg,))
@@ -703,7 +732,6 @@ mips32op("mtc0",    [cpu.bs('010000'), cpu.bs('00100'), rt, cpr0,
                      cpu.bs('00000000'), cpr])
 mips32op("mtc1",    [cpu.bs('010001'), cpu.bs('00100'), rt, fs,
                      cpu.bs('00000000000')])
-
 # XXXX TODO CFC1
 mips32op("cfc1",    [cpu.bs('010001'), cpu.bs('00010'), rt, fs,
                      cpu.bs('00000000000')])
@@ -763,3 +791,33 @@ mips32op("tlbwi",   [cpu.bs('010000'), cpu.bs('1'), cpu.bs('0'*19),
 
 mips32op("teq",     [cpu.bs('000000'), rs, rt, bs_code, cpu.bs('110100')],
          [rs, rt])
+mips32op("tne",     [cpu.bs('000000'), rs, rt, bs_code, cpu.bs('110110')],         
+         [rs, rt])
+
+mips32op("clz",     [cpu.bs('011100'), rs, rt, rd, cpu.bs('00000'), cpu.bs('100000')],
+        [rs, rd])
+mips32op("clz",     [cpu.bs('000000'), rs, cpu.bs('00000'), rd, cpu.bs('00001010000')],
+        [rs, rd])
+
+mips32op("ll",      [cpu.bs('110000'), base, rt, s16imm_noarg], [base, rt])
+mips32op("ll",      [cpu.bs('011111'), base, rt, s09imm_noarg, cpu.bs('0110110')], [base, rt])
+
+mips32op("sc",      [cpu.bs('111000'), base, rt, s16imm_noarg], [base, rt])
+mips32op("sc",      [cpu.bs('011111'), base, rt, s09imm_noarg, cpu.bs('0'), cpu.bs('100110')], [base, rt])
+
+mips32op("sync",    [cpu.bs('000000000000000000000'), stype, cpu.bs('001111')], [stype])
+
+mips32op("pref",    [cpu.bs('110011'), base, hint_pref, s16imm_noarg], [base, hint_pref])
+mips32op("pref",    [cpu.bs('011111'), base, hint_pref, s09imm_noarg, cpu.bs('0110101')], [base, hint_pref])
+
+mips32op("tlbwr",   [cpu.bs('01000010000000000000000000000110')], [])
+mips32op("tlbr",    [cpu.bs('01000010000000000000000000000001')], [])
+
+mips32op("cache",   [cpu.bs('101111'), base, oper, s16imm_noarg], [base, oper])
+mips32op("cache",   [cpu.bs('011111'), base, oper, s09imm_noarg, cpu.bs('0100101')], [base, oper])
+
+mips32op("eret",    [cpu.bs('01000010000000000000000000011000')], [])
+
+mips32op("mtlo",    [cpu.bs('000000'), rs, cpu.bs('000000000000000'), cpu.bs('010011')], [rs])
+mips32op("mthi",    [cpu.bs('000000'), rs, cpu.bs('000000000000000'), cpu.bs('010001')], [rs])
+
diff --git a/miasm/arch/mips32/regs.py b/miasm/arch/mips32/regs.py
index eee17caf..967b7458 100644
--- a/miasm/arch/mips32/regs.py
+++ b/miasm/arch/mips32/regs.py
@@ -71,7 +71,7 @@ cpr0_str[131] = "CONFIG3"
 cpr0_str[132] = "CONFIG4"
 cpr0_str[133] = "CONFIG5"
 cpr0_str[152] = "WATCHHI"
-cpr0_str[250] = "KSCRATCH0"
+cpr0_str[250] = "KSCRATCH"
 cpr0_str[251] = "KSCRATCH1"
 cpr0_str[252] = "KSCRATCH2"
 cpr0_str[253] = "KSCRATCH3"
diff --git a/miasm/arch/mips32/sem.py b/miasm/arch/mips32/sem.py
index 903be3be..669fca13 100644
--- a/miasm/arch/mips32/sem.py
+++ b/miasm/arch/mips32/sem.py
@@ -84,6 +84,11 @@ def lb(arg1, arg2):
     arg1 = mem8[arg2.ptr].signExtend(32)
 
 @sbuild.parse
+def ll(arg1, arg2):
+    "To load a word from memory for an atomic read-modify-write"
+    arg1 = arg2
+
+@sbuild.parse
 def beq(arg1, arg2, arg3):
     "Branches on @arg3 if the quantities of two registers @arg1, @arg2 are eq"
     dst = arg3 if ExprOp(m2_expr.TOK_EQUAL, arg1, arg2) else ExprLoc(ir.get_next_break_loc_key(instr), ir.IRDst.size)
@@ -140,6 +145,14 @@ def nop():
     """Do nothing"""
 
 @sbuild.parse
+def sync(arg1):
+    """Syncronize Shared Memory"""
+
+@sbuild.parse
+def pref(arg1, arg2):
+    """To move data between memory and cache"""
+
+@sbuild.parse
 def j(arg1):
     """Jump to an address @arg1"""
     PC = arg1
@@ -372,6 +385,14 @@ def tlbwi():
 def tlbp():
     "TODO XXX"
 
+@sbuild.parse
+def tlbwr():
+    "TODO XXX"
+
+@sbuild.parse
+def tlbr():
+    "TODO XXX"
+
 def ins(ir, instr, a, b, c, d):
     e = []
     pos = int(c)
@@ -488,6 +509,66 @@ def ei(arg1):
 def ehb(arg1):
     "NOP"
 
+@sbuild.parse
+def sc(arg1, arg2):
+    arg1 = arg2;
+    arg2 = ExprInt(0x1, 32)
+
+@sbuild.parse
+def mthi(arg1):
+    R_HI = arg1
+
+@sbuild.parse
+def mtlo(arg1):
+    R_LOW = arg1
+
+@sbuild.parse
+def clz(rs, rd):
+
+    # Rd <- LeadingZeroDetect(Rs)
+
+    # Invert the value
+    reversed_rs = ~rs
+
+    # Test bits individually
+    b31 = (reversed_rs & i32(2**31)) >> i32(31) if reversed_rs else i32(0)
+    b30 = (reversed_rs & i32(2**30)) >> i32(30) if b31 else i32(0)
+    b29 = (reversed_rs & i32(2**29)) >> i32(29) if b30 else i32(0)
+    b28 = (reversed_rs & i32(2**28)) >> i32(28) if b29 else i32(0)
+    b27 = (reversed_rs & i32(2**27)) >> i32(27) if b28 else i32(0)
+    b26 = (reversed_rs & i32(2**26)) >> i32(26) if b27 else i32(0)
+    b25 = (reversed_rs & i32(2**25)) >> i32(25) if b26 else i32(0)
+    b24 = (reversed_rs & i32(2**24)) >> i32(24) if b25 else i32(0)
+    b23 = (reversed_rs & i32(2**23)) >> i32(23) if b24 else i32(0)
+    b22 = (reversed_rs & i32(2**22)) >> i32(22) if b23 else i32(0)
+    b21 = (reversed_rs & i32(2**21)) >> i32(21) if b22 else i32(0)
+    b20 = (reversed_rs & i32(2**20)) >> i32(20) if b21 else i32(0)
+    b19 = (reversed_rs & i32(2**19)) >> i32(19) if b20 else i32(0)
+    b18 = (reversed_rs & i32(2**18)) >> i32(18) if b19 else i32(0)
+    b17 = (reversed_rs & i32(2**17)) >> i32(17) if b18 else i32(0)
+    b16 = (reversed_rs & i32(2**16)) >> i32(16) if b17 else i32(0)
+    b15 = (reversed_rs & i32(2**15)) >> i32(15) if b16 else i32(0)
+    b14 = (reversed_rs & i32(2**14)) >> i32(14) if b15 else i32(0)
+    b13 = (reversed_rs & i32(2**13)) >> i32(13) if b14 else i32(0)
+    b12 = (reversed_rs & i32(2**12)) >> i32(12) if b13 else i32(0)
+    b11 = (reversed_rs & i32(2**11)) >> i32(11) if b12 else i32(0)
+    b10 = (reversed_rs & i32(2**10)) >> i32(10) if b11 else i32(0)
+    b09 = (reversed_rs & i32(2 ** 9)) >> i32(9) if b10 else i32(0)
+    b08 = (reversed_rs & i32(2 ** 8)) >> i32(8) if b09 else i32(0)
+    b07 = (reversed_rs & i32(2 ** 7)) >> i32(7) if b08 else i32(0)
+    b06 = (reversed_rs & i32(2 ** 6)) >> i32(6) if b07 else i32(0)
+    b05 = (reversed_rs & i32(2 ** 5)) >> i32(5) if b06 else i32(0)
+    b04 = (reversed_rs & i32(2 ** 4)) >> i32(4) if b05 else i32(0)
+    b03 = (reversed_rs & i32(2 ** 3)) >> i32(3) if b04 else i32(0)
+    b02 = (reversed_rs & i32(2 ** 2)) >> i32(2) if b03 else i32(0)
+    b01 = (reversed_rs & i32(2 ** 1)) >> i32(1) if b02 else i32(0)
+    b00 = (reversed_rs & i32(2 ** 0)) >> i32(0) if b01 else i32(0)
+
+    # Sum all partial results
+    rd = b31 + b30 + b29 + b28 + b27 + b26 + b25 + b24 + b23 + b22 + b21 + b20 \
+        + b19 + b18 + b17 + b16 + b15 + b14 + b13 + b12 + b11 + b10 + b09 + b08 \
+        + b07 + b06 + b05 + b04 + b03 + b02 + b01 + b00
+
 def teq(ir, instr, arg1, arg2):
     e = []
 
@@ -499,7 +580,7 @@ def teq(ir, instr, arg1, arg2):
     do_except.append(m2_expr.ExprAssign(exception_flags, m2_expr.ExprInt(
         EXCEPT_DIV_BY_ZERO, exception_flags.size)))
     do_except.append(m2_expr.ExprAssign(ir.IRDst, loc_next_expr))
-    blk_except = IRBlock(loc_except.index, [AssignBlock(do_except, instr)])
+    blk_except = IRBlock(loc_except, [AssignBlock(do_except, instr)])
 
     cond = arg1 - arg2
 
@@ -510,6 +591,28 @@ def teq(ir, instr, arg1, arg2):
 
     return e, [blk_except]
 
+def tne(ir, instr, arg1, arg2):
+    e = []
+
+    loc_except, loc_except_expr = ir.gen_loc_key_and_expr(ir.IRDst.size)
+    loc_next = ir.get_next_loc_key(instr)
+    loc_next_expr = m2_expr.ExprLoc(loc_next, ir.IRDst.size)
+
+    do_except = []
+    do_except.append(m2_expr.ExprAssign(exception_flags, m2_expr.ExprInt(
+        EXCEPT_DIV_BY_ZERO, exception_flags.size)))
+    do_except.append(m2_expr.ExprAssign(ir.IRDst, loc_next_expr))
+    blk_except = IRBlock(loc_except, [AssignBlock(do_except, instr)])
+
+    cond = arg1 ^ arg2
+
+
+    e = []
+    e.append(m2_expr.ExprAssign(ir.IRDst,
+                             m2_expr.ExprCond(cond, loc_next_expr, loc_except_expr)))
+
+    return e, [blk_except]
+
 
 mnemo_func = sbuild.functions
 mnemo_func.update({
@@ -536,8 +639,9 @@ mnemo_func.update({
         'subu': l_sub,
         'xor': l_xor,
         'xori': l_xor,
-        'teq': teq
-})
+        'teq': teq,
+        'tne': tne
+        })
 
 def get_mnemo_expr(ir, instr, *args):
     instr, extra_ir = mnemo_func[instr.name.lower()](ir, instr, *args)