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| author | Camille Mougey <commial@gmail.com> | 2018-09-11 08:41:21 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-09-11 08:41:21 +0200 |
| commit | 1b414b19fa6bba8e565d33cffe73fda569bf1479 (patch) | |
| tree | ab621dce8518980d1e5bae5d861a060f98160e9f | |
| parent | 8e6b39d80e9f8db8389bd2a8106d0f64b91c19e9 (diff) | |
| parent | deb20acf06374cec650188d55e6a4239007eb086 (diff) | |
| download | miasm-1b414b19fa6bba8e565d33cffe73fda569bf1479.tar.gz miasm-1b414b19fa6bba8e565d33cffe73fda569bf1479.zip | |
Merge pull request #850 from serpilliere/fix_aam
Fix aam
| -rw-r--r-- | miasm2/arch/x86/sem.py | 39 |
1 files changed, 23 insertions, 16 deletions
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index 0cb9f3e2..f07e2285 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -3115,15 +3115,28 @@ def das(_, instr): return e, [] -def aam(_, instr, src): +def aam(ir, instr, src): e = [] - tempAL = mRAX[instr.mode][0:8] - newEAX = m2_expr.ExprCompose(m2_expr.ExprOp("umod", tempAL, src), - m2_expr.ExprOp("udiv", tempAL, src), - mRAX[instr.mode][16:]) - e += [m2_expr.ExprAff(mRAX[instr.mode], newEAX)] - e += update_flag_arith(newEAX) - e.append(m2_expr.ExprAff(af, m2_expr.ExprInt(0, 1))) + assert src.is_int() + + value = int(src) + if value: + tempAL = mRAX[instr.mode][0:8] + newEAX = m2_expr.ExprCompose( + m2_expr.ExprOp("umod", tempAL, src), + m2_expr.ExprOp("udiv", tempAL, src), + mRAX[instr.mode][16:] + ) + e += [m2_expr.ExprAff(mRAX[instr.mode], newEAX)] + e += update_flag_arith(newEAX) + e.append(m2_expr.ExprAff(af, m2_expr.ExprInt(0, 1))) + else: + e.append( + m2_expr.ExprAff( + exception_flags, + m2_expr.ExprInt(EXCEPT_DIV_BY_ZERO, exception_flags.size) + ) + ) return e, [] @@ -3668,18 +3681,12 @@ def xorps(_, instr, dst, src): def rdmsr(ir, instr): - msr_addr = m2_expr.ExprId('MSR', 64) + m2_expr.ExprInt(8, 64) * mRCX[32].zeroExtend(64) - e = [] - e.append(m2_expr.ExprAff(mRAX[32], ir.ExprMem(msr_addr, 32))) - e.append(m2_expr.ExprAff(mRDX[32], ir.ExprMem(msr_addr + m2_expr.ExprInt(4, 64), 32))) + e = [m2_expr.ExprAff(exception_flags,m2_expr.ExprInt(EXCEPT_PRIV_INSN, 32))] return e, [] def wrmsr(ir, instr): - msr_addr = m2_expr.ExprId('MSR', 64) + m2_expr.ExprInt(8, 64) * mRCX[32].zeroExtend(64) - e = [] - src = m2_expr.ExprCompose(mRAX[32], mRDX[32]) - e.append(m2_expr.ExprAff(ir.ExprMem(msr_addr, 64), src)) + e = [m2_expr.ExprAff(exception_flags,m2_expr.ExprInt(EXCEPT_PRIV_INSN, 32))] return e, [] # MMX/SSE/AVX operations |