Rename ir_arch for jitter

18 files changed, 167 insertions, 156 deletions

diff --git a/example/symbol_exec/dse_crackme.py b/example/symbol_exec/dse_crackme.py
index cdaf5a1a..fc2e1414 100644
--- a/example/symbol_exec/dse_crackme.py
+++ b/example/symbol_exec/dse_crackme.py
@@ -80,10 +80,10 @@ loc_db = LocationDB()
 sb = Sandbox_Linux_x86_64(loc_db, options.filename, options, globals())
 
 # Init segment
-sb.jitter.ir_arch.do_stk_segm = True
-sb.jitter.ir_arch.do_ds_segm = True
-sb.jitter.ir_arch.do_str_segm = True
-sb.jitter.ir_arch.do_all_segm = True
+sb.jitter.lifter.do_stk_segm = True
+sb.jitter.lifter.do_ds_segm = True
+sb.jitter.lifter.do_str_segm = True
+sb.jitter.lifter.do_all_segm = True
 FS_0_ADDR = 0x7ff70000
 sb.jitter.cpu.FS = 0x4
 sb.jitter.cpu.set_segm_base(sb.jitter.cpu.FS, FS_0_ADDR)
diff --git a/example/symbol_exec/dse_strategies.py b/example/symbol_exec/dse_strategies.py
index bcea2329..933a51db 100644
--- a/example/symbol_exec/dse_strategies.py
+++ b/example/symbol_exec/dse_strategies.py
@@ -79,7 +79,7 @@ dse = DSEPathConstraint(machine, loc_db, produce_solution=strategy)
 dse.attach(jitter)
 # Concretize everything except the argument
 dse.update_state_from_concrete()
-regs = jitter.ir_arch.arch.regs
+regs = jitter.lifter.arch.regs
 arg = ExprId("ARG", 32)
 arg_addr = ExprMem(ExprInt(jitter.cpu.ESP + 4, regs.ESP.size), arg.size)
 dse.update_state({
diff --git a/miasm/analysis/debugging.py b/miasm/analysis/debugging.py
index 3cbbf482..56ef8646 100644
--- a/miasm/analysis/debugging.py
+++ b/miasm/analysis/debugging.py
@@ -212,7 +212,7 @@ class Debugguer(object):
     def set_reg_value(self, reg_name, value):
 
         # Handle PC case
-        if reg_name == self.myjit.ir_arch.pc.name:
+        if reg_name == self.myjit.lifter.pc.name:
             self.init_run(value)
 
         setattr(self.myjit.cpu, reg_name, value)
diff --git a/miasm/analysis/sandbox.py b/miasm/analysis/sandbox.py
index 2c56e7ca..542e31f9 100644
--- a/miasm/analysis/sandbox.py
+++ b/miasm/analysis/sandbox.py
@@ -390,10 +390,10 @@ class Arch_x86(Arch):
         super(Arch_x86, self).__init__(loc_db, **kwargs)
 
         if self.options.usesegm:
-            self.jitter.ir_arch.do_stk_segm = True
-            self.jitter.ir_arch.do_ds_segm = True
-            self.jitter.ir_arch.do_str_segm = True
-            self.jitter.ir_arch.do_all_segm = True
+            self.jitter.lifter.do_stk_segm = True
+            self.jitter.lifter.do_ds_segm = True
+            self.jitter.lifter.do_str_segm = True
+            self.jitter.lifter.do_all_segm = True
 
         # Init stack
         self.jitter.stack_size = self.STACK_SIZE
diff --git a/miasm/arch/arm/jit.py b/miasm/arch/arm/jit.py
index 78a69027..27c26988 100644
--- a/miasm/arch/arm/jit.py
+++ b/miasm/arch/arm/jit.py
@@ -33,14 +33,14 @@ class arm_CGen(CGen):
 
             if instr.name.startswith("IT"):
                 assignments = []
-                label = self.ir_arch.get_instr_label(instr)
+                label = self.lifter.get_instr_label(instr)
                 irblocks = []
-                index, irblocks = self.ir_arch.do_it_block(label, index, block, assignments, True)
+                index, irblocks = self.lifter.do_it_block(label, index, block, assignments, True)
                 irblocks_list += irblocks
                 continue
 
 
-            assignblk_head, assignblks_extra = self.ir_arch.instr2ir(instr)
+            assignblk_head, assignblks_extra = self.lifter.instr2ir(instr)
             # Keep result in ordered list as first element is the assignblk head
             # The remainings order is not really important
             irblock_head = self.assignblk_to_irbloc(instr, assignblk_head)
diff --git a/miasm/arch/mep/jit.py b/miasm/arch/mep/jit.py
index e3cd2428..3fee2537 100644
--- a/miasm/arch/mep/jit.py
+++ b/miasm/arch/mep/jit.py
@@ -24,10 +24,10 @@ class mep_CGen(CGen):
     Note: it is used to emulate the *REPEAT instructions
     """
 
-    def __init__(self, ir_arch):
-        self.ir_arch = ir_arch
-        self.PC = self.ir_arch.arch.regs.PC
-        self.translator = TranslatorC(self.ir_arch.loc_db)
+    def __init__(self, lifter):
+        self.lifter = lifter
+        self.PC = self.lifter.arch.regs.PC
+        self.translator = TranslatorC(self.lifter.loc_db)
         self.init_arch_C()
 
     def gen_pre_code(self, attrib):
@@ -79,7 +79,7 @@ class jitter_mepl(Jitter):
     def __init__(self, loc_db, *args, **kwargs):
         Jitter.__init__(self, Lifter_MEPl(loc_db), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
+        self.lifter.jit_pc = self.lifter.arch.regs.PC
 
     def push_uint16_t(self, v):
         regs = self.cpu.get_gpreg()
@@ -109,4 +109,4 @@ class jitter_mepb(jitter_mepl):
     def __init__(self, loc_db, *args, **kwargs):
         Jitter.__init__(self, Lifter_MEPb(loc_db), *args, **kwargs)
         self.vm.set_big_endian()
-        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
+        self.lifter.jit_pc = self.lifter.arch.regs.PC
diff --git a/miasm/arch/mips32/jit.py b/miasm/arch/mips32/jit.py
index 779c2b77..53f48303 100644
--- a/miasm/arch/mips32/jit.py
+++ b/miasm/arch/mips32/jit.py
@@ -34,8 +34,8 @@ class mipsCGen(CGen):
     return JIT_RET_NO_EXCEPTION;
     """
 
-    def __init__(self, ir_arch):
-        super(mipsCGen, self).__init__(ir_arch)
+    def __init__(self, lifter):
+        super(mipsCGen, self).__init__(lifter)
         self.delay_slot_dst = m2_expr.ExprId("branch_dst_irdst", 32)
         self.delay_slot_set = m2_expr.ExprId("branch_dst_set", 32)
 
@@ -49,17 +49,17 @@ class mipsCGen(CGen):
 
                 irs = []
                 for assignblock in irblock:
-                    if self.ir_arch.pc not in assignblock:
+                    if self.lifter.pc not in assignblock:
                         irs.append(AssignBlock(assignments, assignblock.instr))
                         continue
                     assignments = dict(assignblock)
                     # Add internal branch destination
                     assignments[self.delay_slot_dst] = assignblock[
-                        self.ir_arch.pc]
+                        self.lifter.pc]
                     assignments[self.delay_slot_set] = m2_expr.ExprInt(1, 32)
                     # Replace IRDst with next instruction
-                    dst_loc_key = self.ir_arch.get_next_instr(assignblock.instr)
-                    assignments[self.ir_arch.IRDst] = m2_expr.ExprLoc(dst_loc_key, 32)
+                    dst_loc_key = self.lifter.get_next_instr(assignblock.instr)
+                    assignments[self.lifter.IRDst] = m2_expr.ExprLoc(dst_loc_key, 32)
                     irs.append(AssignBlock(assignments, assignblock.instr))
                 irblocks[blk_idx] = IRBlock(irblock.loc_db, irblock.loc_key, irs)
 
@@ -71,7 +71,7 @@ class mipsCGen(CGen):
         """
 
         loc_key = self.get_block_post_label(block)
-        offset = self.ir_arch.loc_db.get_location_offset(loc_key)
+        offset = self.lifter.loc_db.get_location_offset(loc_key)
         out = (self.CODE_RETURN_NO_EXCEPTION % (loc_key,
                                                 self.C_PC,
                                                 m2_expr.ExprId('branch_dst_irdst', 32),
diff --git a/miasm/arch/x86/jit.py b/miasm/arch/x86/jit.py
index 38301e3c..a90dec07 100644
--- a/miasm/arch/x86/jit.py
+++ b/miasm/arch/x86/jit.py
@@ -14,10 +14,10 @@ log.setLevel(logging.CRITICAL)
 
 
 class x86_32_CGen(CGen):
-    def __init__(self, ir_arch):
-        self.ir_arch = ir_arch
-        self.PC = self.ir_arch.arch.regs.RIP
-        self.translator = TranslatorC(self.ir_arch.loc_db)
+    def __init__(self, lifter):
+        self.lifter = lifter
+        self.PC = self.lifter.arch.regs.RIP
+        self.translator = TranslatorC(self.lifter.loc_db)
         self.init_arch_C()
 
     def gen_post_code(self, attrib, pc_value):
@@ -44,20 +44,20 @@ class jitter_x86_16(Jitter):
     def __init__(self, loc_db, *args, **kwargs):
         Jitter.__init__(self, Lifter_X86_16(loc_db), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.do_stk_segm = False
-        self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
-        self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
+        self.lifter.do_stk_segm = False
+        self.orig_irbloc_fix_regs_for_mode = self.lifter.irbloc_fix_regs_for_mode
+        self.lifter.irbloc_fix_regs_for_mode = self.lifterbloc_fix_regs_for_mode
 
-    def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64):
+    def lifterbloc_fix_regs_for_mode(self, irblock, attrib=64):
         return self.orig_irbloc_fix_regs_for_mode(irblock, 64)
 
     def push_uint16_t(self, value):
-        self.cpu.SP -= self.ir_arch.sp.size // 8
+        self.cpu.SP -= self.lifter.sp.size // 8
         self.vm.set_u16(self.cpu.SP, value)
 
     def pop_uint16_t(self):
         value = self.vm.get_u16(self.cpu.SP)
-        self.cpu.SP += self.ir_arch.sp.size // 8
+        self.cpu.SP += self.lifter.sp.size // 8
         return value
 
     def get_stack_arg(self, index):
@@ -75,30 +75,30 @@ class jitter_x86_32(Jitter):
     def __init__(self, loc_db, *args, **kwargs):
         Jitter.__init__(self, Lifter_X86_32(loc_db), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.do_stk_segm = False
+        self.lifter.do_stk_segm = False
 
-        self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
-        self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
+        self.orig_irbloc_fix_regs_for_mode = self.lifter.irbloc_fix_regs_for_mode
+        self.lifter.irbloc_fix_regs_for_mode = self.lifterbloc_fix_regs_for_mode
 
-    def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64):
+    def lifterbloc_fix_regs_for_mode(self, irblock, attrib=64):
         return self.orig_irbloc_fix_regs_for_mode(irblock, 64)
 
     def push_uint16_t(self, value):
-        self.cpu.ESP -= self.ir_arch.sp.size // 8
+        self.cpu.ESP -= self.lifter.sp.size // 8
         self.vm.set_u16(self.cpu.ESP, value)
 
     def pop_uint16_t(self):
         value = self.vm.get_u16(self.cpu.ESP)
-        self.cpu.ESP += self.ir_arch.sp.size // 8
+        self.cpu.ESP += self.lifter.sp.size // 8
         return value
 
     def push_uint32_t(self, value):
-        self.cpu.ESP -= self.ir_arch.sp.size // 8
+        self.cpu.ESP -= self.lifter.sp.size // 8
         self.vm.set_u32(self.cpu.ESP, value)
 
     def pop_uint32_t(self):
         value = self.vm.get_u32(self.cpu.ESP)
-        self.cpu.ESP += self.ir_arch.sp.size // 8
+        self.cpu.ESP += self.lifter.sp.size // 8
         return value
 
     def get_stack_arg(self, index):
@@ -201,21 +201,21 @@ class jitter_x86_64(Jitter):
     def __init__(self, loc_db, *args, **kwargs):
         Jitter.__init__(self, Lifter_X86_64(loc_db), *args, **kwargs)
         self.vm.set_little_endian()
-        self.ir_arch.do_stk_segm = False
+        self.lifter.do_stk_segm = False
 
-        self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
-        self.ir_arch.irbloc_fix_regs_for_mode = self.ir_archbloc_fix_regs_for_mode
+        self.orig_irbloc_fix_regs_for_mode = self.lifter.irbloc_fix_regs_for_mode
+        self.lifter.irbloc_fix_regs_for_mode = self.lifterbloc_fix_regs_for_mode
 
-    def ir_archbloc_fix_regs_for_mode(self, irblock, attrib=64):
+    def lifterbloc_fix_regs_for_mode(self, irblock, attrib=64):
         return self.orig_irbloc_fix_regs_for_mode(irblock, 64)
 
     def push_uint64_t(self, value):
-        self.cpu.RSP -= self.ir_arch.sp.size // 8
+        self.cpu.RSP -= self.lifter.sp.size // 8
         self.vm.set_u64(self.cpu.RSP, value)
 
     def pop_uint64_t(self):
         value = self.vm.get_u64(self.cpu.RSP)
-        self.cpu.RSP += self.ir_arch.sp.size // 8
+        self.cpu.RSP += self.lifter.sp.size // 8
         return value
 
     def get_stack_arg(self, index):
diff --git a/miasm/jitter/codegen.py b/miasm/jitter/codegen.py
index d05865f2..305d6c36 100644
--- a/miasm/jitter/codegen.py
+++ b/miasm/jitter/codegen.py
@@ -3,6 +3,7 @@ Module to generate C code for a given native @block
 """
 
 from builtins import zip
+import warnings
 
 from future.utils import viewitems, viewvalues
 
@@ -107,16 +108,21 @@ class CGen(object):
     CPU_exception_flag = EXCEPT_UNK_MNEMO;
     """ + CODE_RETURN_EXCEPTION
 
-    def __init__(self, ir_arch):
-        self.ir_arch = ir_arch
-        self.PC = self.ir_arch.pc
-        self.translator = TranslatorC(self.ir_arch.loc_db)
+    def __init__(self, lifter):
+        self.lifter = lifter
+        self.PC = self.lifter.pc
+        self.translator = TranslatorC(self.lifter.loc_db)
         self.init_arch_C()
 
+    @property
+    def ir_arch(self):
+        warnings.warn('DEPRECATION WARNING: use ".lifter" instead of ".ir_arch"')
+        return self.lifter
+
     def init_arch_C(self):
         """Iinitialize jitter internals"""
         self.id_to_c_id = {}
-        for reg in self.ir_arch.arch.regs.all_regs_ids:
+        for reg in self.lifter.arch.regs.all_regs_ids:
             self.id_to_c_id[reg] = ExprId('mycpu->%s' % reg, reg.size)
 
         self.C_PC = self.id_to_c(self.PC)
@@ -150,13 +156,13 @@ class CGen(object):
         @assignblk: Assignblk instance
         """
         new_assignblk = dict(assignblk)
-        if self.ir_arch.IRDst not in assignblk:
+        if self.lifter.IRDst not in assignblk:
             offset = instr.offset + instr.l
-            loc_key = self.ir_arch.loc_db.get_or_create_offset_location(offset)
-            dst = ExprLoc(loc_key, self.ir_arch.IRDst.size)
-            new_assignblk[self.ir_arch.IRDst] = dst
+            loc_key = self.lifter.loc_db.get_or_create_offset_location(offset)
+            dst = ExprLoc(loc_key, self.lifter.IRDst.size)
+            new_assignblk[self.lifter.IRDst] = dst
         irs = [AssignBlock(new_assignblk, instr)]
-        return IRBlock(self.ir_arch.loc_db, self.ir_arch.get_loc_key_for_instr(instr), irs)
+        return IRBlock(self.lifter.loc_db, self.lifter.get_loc_key_for_instr(instr), irs)
 
     def block2assignblks(self, block):
         """
@@ -165,7 +171,7 @@ class CGen(object):
         """
         irblocks_list = []
         for instr in block.lines:
-            assignblk_head, assignblks_extra = self.ir_arch.instr2ir(instr)
+            assignblk_head, assignblks_extra = self.lifter.instr2ir(instr)
             # Keep result in ordered list as first element is the assignblk head
             # The remainings order is not really important
             irblock_head = self.assignblk_to_irbloc(instr, assignblk_head)
@@ -174,7 +180,7 @@ class CGen(object):
             # Simplify high level operators
             out = []
             for irblock in irblocks:
-                new_irblock = self.ir_arch.irbloc_fix_regs_for_mode(irblock, self.ir_arch.attrib)
+                new_irblock = self.lifter.irbloc_fix_regs_for_mode(irblock, self.lifter.attrib)
                 new_irblock = new_irblock.simplify(expr_simp_high_to_explicit)[1]
                 out.append(new_irblock)
             irblocks = out
@@ -255,11 +261,11 @@ class CGen(object):
 
         for dst, src in viewitems(assignblk):
             src = src.replace_expr(prefetchers)
-            if dst == self.ir_arch.IRDst:
+            if dst == self.lifter.IRDst:
                 pass
             elif isinstance(dst, ExprId):
                 new_dst = self.add_local_var(dst_var, dst_index, dst)
-                if dst in self.ir_arch.arch.regs.regs_flt_expr:
+                if dst in self.lifter.arch.regs.regs_flt_expr:
                     # Don't mask float assignment
                     c_main.append(
                         '%s = (%s);' % (self.id_to_c(new_dst), self.id_to_c(src)))
@@ -299,7 +305,7 @@ class CGen(object):
                 raise ValueError("Unknown dst")
 
         for dst, new_dst in viewitems(dst_var):
-            if dst == self.ir_arch.IRDst:
+            if dst == self.lifter.IRDst:
                 continue
 
             c_updt.append('%s = %s;' % (self.id_to_c(dst), self.id_to_c(new_dst)))
@@ -339,13 +345,13 @@ class CGen(object):
                     "((%s)?(%s):(%s))" % (cond, src1b, src2b))
         if isinstance(expr, ExprInt):
             offset = int(expr)
-            loc_key = self.ir_arch.loc_db.get_or_create_offset_location(offset)
+            loc_key = self.lifter.loc_db.get_or_create_offset_location(offset)
             self.add_label_index(dst2index, loc_key)
             out = hex(offset)
             return ("%s" % dst2index[loc_key], out)
         if expr.is_loc():
             loc_key = expr.loc_key
-            offset = self.ir_arch.loc_db.get_location_offset(expr.loc_key)
+            offset = self.lifter.loc_db.get_location_offset(expr.loc_key)
             if offset is not None:
                 self.add_label_index(dst2index, loc_key)
                 out = hex(offset)
@@ -391,7 +397,7 @@ class CGen(object):
             out.append(
                 'printf("%.8X %s\\n");' % (
                     instr_attrib.instr.offset,
-                    instr_attrib.instr.to_string(self.ir_arch.loc_db)
+                    instr_attrib.instr.to_string(self.lifter.loc_db)
                 )
             )
         return out
@@ -421,7 +427,7 @@ class CGen(object):
             return out
 
         assert isinstance(dst, LocKey)
-        offset = self.ir_arch.loc_db.get_location_offset(dst)
+        offset = self.lifter.loc_db.get_location_offset(dst)
         if offset is None:
             # Generate goto for local labels
             return ['goto %s;' % dst]
@@ -523,7 +529,7 @@ class CGen(object):
         """
 
         # Check explicit exception raising
-        attrib.set_exception = self.ir_arch.arch.regs.exception_flags in assignblk
+        attrib.set_exception = self.lifter.arch.regs.exception_flags in assignblk
 
         element_read = assignblk.get_r(mem_read=True)
         # Check mem read
@@ -572,7 +578,7 @@ class CGen(object):
 
         last_instr = block.lines[-1]
         offset = last_instr.offset + last_instr.l
-        return self.ir_arch.loc_db.get_or_create_offset_location(offset)
+        return self.lifter.loc_db.get_or_create_offset_location(offset)
 
     def gen_init(self, block):
         """
@@ -582,7 +588,7 @@ class CGen(object):
 
         instr_offsets = [line.offset for line in block.lines]
         post_label = self.get_block_post_label(block)
-        post_offset = self.ir_arch.loc_db.get_location_offset(post_label)
+        post_offset = self.lifter.loc_db.get_location_offset(post_label)
         instr_offsets.append(post_offset)
         lbl_start = block.loc_key
         return (self.CODE_INIT % lbl_start).split("\n"), instr_offsets
@@ -618,7 +624,7 @@ class CGen(object):
         """
 
         loc_key = self.get_block_post_label(block)
-        offset = self.ir_arch.loc_db.get_location_offset(loc_key)
+        offset = self.lifter.loc_db.get_location_offset(loc_key)
         dst = self.dst_to_c(offset)
         code = self.CODE_RETURN_NO_EXCEPTION % (loc_key, self.C_PC, dst, dst)
         return code.split('\n')
diff --git a/miasm/jitter/jitcore.py b/miasm/jitter/jitcore.py
index a6c9dda6..434854ca 100644
--- a/miasm/jitter/jitcore.py
+++ b/miasm/jitter/jitcore.py
@@ -37,15 +37,15 @@ class JitCore(object):
     jitted_block_delete_cb = None
     jitted_block_max_size = 10000
 
-    def __init__(self, ir_arch, bin_stream):
+    def __init__(self, lifter, bin_stream):
         """Initialise a JitCore instance.
-        @ir_arch: ir instance for current architecture
+        @lifter: Lifter instance for current architecture
         @bin_stream: bin_stream instance
         """
         # Arch related
-        self.ir_arch = ir_arch
-        self.ircfg = self.ir_arch.new_ircfg()
-        self.arch_name = "%s%s" % (self.ir_arch.arch.name, self.ir_arch.attrib)
+        self.lifter = lifter
+        self.ircfg = self.lifter.new_ircfg()
+        self.arch_name = "%s%s" % (self.lifter.arch.name, self.lifter.attrib)
 
         # Structures for block tracking
         self.offset_to_jitted_func = BoundedDict(self.jitted_block_max_size,
@@ -64,14 +64,19 @@ class JitCore(object):
         # Disassembly Engine
         self.split_dis = set()
         self.mdis = disasmEngine(
-            ir_arch.arch, ir_arch.attrib, bin_stream,
+            lifter.arch, lifter.attrib, bin_stream,
             lines_wd=self.options["jit_maxline"],
-            loc_db=ir_arch.loc_db,
+            loc_db=lifter.loc_db,
             follow_call=False,
             dontdis_retcall=False,
             split_dis=self.split_dis,
         )
 
+    @property
+    def ir_arch(self):
+        warnings.warn('DEPRECATION WARNING: use ".lifter" instead of ".ir_arch"')
+        return self.lifter
+
 
     def set_options(self, **kwargs):
         "Set options relative to the backend"
@@ -104,7 +109,7 @@ class JitCore(object):
             cur_block.ad_max = cur_block.lines[-1].offset + cur_block.lines[-1].l
         else:
             # 1 byte block for unknown mnemonic
-            offset = self.ir_arch.loc_db.get_location_offset(cur_block.loc_key)
+            offset = self.lifter.loc_db.get_location_offset(cur_block.loc_key)
             cur_block.ad_min = offset
             cur_block.ad_max = offset+1
 
@@ -131,7 +136,7 @@ class JitCore(object):
 
         # Get the block
         if isinstance(addr, LocKey):
-            addr = self.ir_arch.loc_db.get_location_offset(addr)
+            addr = self.lifter.loc_db.get_location_offset(addr)
             if addr is None:
                 raise RuntimeError("Unknown offset for LocKey")
 
@@ -172,7 +177,7 @@ class JitCore(object):
         """
 
         if offset is None:
-            offset = getattr(cpu, self.ir_arch.pc.name)
+            offset = getattr(cpu, self.lifter.pc.name)
 
         if offset not in self.offset_to_jitted_func:
             # Need to JiT the block
@@ -237,13 +242,13 @@ class JitCore(object):
             try:
                 for irblock in block.blocks:
                     # Remove offset -> jitted block link
-                    offset = self.ir_arch.loc_db.get_location_offset(irblock.loc_key)
+                    offset = self.lifter.loc_db.get_location_offset(irblock.loc_key)
                     if offset in self.offset_to_jitted_func:
                         del(self.offset_to_jitted_func[offset])
 
             except AttributeError:
                 # The block has never been translated in IR
-                offset = self.ir_arch.loc_db.get_location_offset(block.loc_key)
+                offset = self.lifter.loc_db.get_location_offset(block.loc_key)
                 if offset in self.offset_to_jitted_func:
                     del(self.offset_to_jitted_func[offset])
 
@@ -280,7 +285,7 @@ class JitCore(object):
         @block: asmblock
         """
         block_raw = b"".join(line.b for line in block.lines)
-        offset = self.ir_arch.loc_db.get_location_offset(block.loc_key)
+        offset = self.lifter.loc_db.get_location_offset(block.loc_key)
         block_hash = md5(
             b"%X_%s_%s_%s_%s" % (
                 offset,
diff --git a/miasm/jitter/jitcore_cc_base.py b/miasm/jitter/jitcore_cc_base.py
index afb2876c..a6c7607a 100644
--- a/miasm/jitter/jitcore_cc_base.py
+++ b/miasm/jitter/jitcore_cc_base.py
@@ -51,11 +51,11 @@ class resolver(object):
 class JitCore_Cc_Base(JitCore):
     "JiT management, abstract class using a C compiler as backend"
 
-    def __init__(self, ir_arch, bin_stream):
+    def __init__(self, lifter, bin_stream):
         self.jitted_block_delete_cb = self.deleteCB
-        super(JitCore_Cc_Base, self).__init__(ir_arch, bin_stream)
+        super(JitCore_Cc_Base, self).__init__(lifter, bin_stream)
         self.resolver = resolver()
-        self.ir_arch = ir_arch
+        self.lifter = lifter
         self.states = {}
         self.tempdir = os.path.join(tempfile.gettempdir(), "miasm_cache")
         try:
@@ -89,7 +89,7 @@ class JitCore_Cc_Base(JitCore):
             os.path.join(
                 lib_dir,
                 "arch",
-                "JitCore_%s%s" % (self.ir_arch.arch.name, ext)
+                "JitCore_%s%s" % (self.lifter.arch.name, ext)
             )
         ]
 
@@ -121,8 +121,8 @@ class JitCore_Cc_Base(JitCore):
         out = [f_declaration + '{'] + out + ['}\n']
         c_code = out
 
-        return self.gen_C_source(self.ir_arch, c_code)
+        return self.gen_C_source(self.lifter, c_code)
 
     @staticmethod
-    def gen_C_source(ir_arch, func_code):
+    def gen_C_source(lifter, func_code):
         raise NotImplementedError()
diff --git a/miasm/jitter/jitcore_gcc.py b/miasm/jitter/jitcore_gcc.py
index 7ffef69e..365e00f7 100644
--- a/miasm/jitter/jitcore_gcc.py
+++ b/miasm/jitter/jitcore_gcc.py
@@ -17,8 +17,8 @@ is_win = platform.system() == "Windows"
 class JitCore_Gcc(JitCore_Cc_Base):
     "JiT management, using a C compiler as backend"
 
-    def __init__(self, ir_arch, bin_stream):
-        super(JitCore_Gcc, self).__init__(ir_arch, bin_stream)
+    def __init__(self, lifter, bin_stream):
+        super(JitCore_Gcc, self).__init__(lifter, bin_stream)
         self.exec_wrapper = Jitgcc.gcc_exec_block
 
     def deleteCB(self, offset):
@@ -37,7 +37,7 @@ class JitCore_Gcc(JitCore_Cc_Base):
         lib = ctypes.cdll.LoadLibrary(fname_so)
         func = getattr(lib, self.FUNCNAME)
         addr = ctypes.cast(func, ctypes.c_void_p).value
-        offset = self.ir_arch.loc_db.get_location_offset(label)
+        offset = self.lifter.loc_db.get_location_offset(label)
         self.offset_to_jitted_func[offset] = addr
         self.states[offset] = lib
 
@@ -133,10 +133,10 @@ class JitCore_Gcc(JitCore_Cc_Base):
         self.load_code(block.loc_key, fname_out)
 
     @staticmethod
-    def gen_C_source(ir_arch, func_code):
+    def gen_C_source(lifter, func_code):
         c_source = ""
         c_source += "\n".join(func_code)
 
-        c_source = gen_core(ir_arch.arch, ir_arch.attrib) + c_source
+        c_source = gen_core(lifter.arch, lifter.attrib) + c_source
         c_source = "#define PARITY_IMPORT\n#include <Python.h>\n" + c_source
         return c_source
diff --git a/miasm/jitter/jitcore_llvm.py b/miasm/jitter/jitcore_llvm.py
index df7d5950..4f1871b2 100644
--- a/miasm/jitter/jitcore_llvm.py
+++ b/miasm/jitter/jitcore_llvm.py
@@ -28,8 +28,8 @@ class JitCore_LLVM(jitcore.JitCore):
         "ppc32": "JitCore_ppc32",
     }
 
-    def __init__(self, ir_arch, bin_stream):
-        super(JitCore_LLVM, self).__init__(ir_arch, bin_stream)
+    def __init__(self, lifter, bin_stream):
+        super(JitCore_LLVM, self).__init__(lifter, bin_stream)
 
         self.options.update(
             {
@@ -41,7 +41,7 @@ class JitCore_LLVM(jitcore.JitCore):
         )
 
         self.exec_wrapper = Jitllvm.llvm_exec_block
-        self.ir_arch = ir_arch
+        self.lifter = lifter
 
         # Cache temporary dir
         self.tempdir = os.path.join(tempfile.gettempdir(), "miasm_cache")
@@ -72,23 +72,23 @@ class JitCore_LLVM(jitcore.JitCore):
         lib_dir = os.path.join(lib_dir, 'arch')
         try:
             jit_lib = os.path.join(
-                lib_dir, self.arch_dependent_libs[self.ir_arch.arch.name] + ext
+                lib_dir, self.arch_dependent_libs[self.lifter.arch.name] + ext
             )
             libs_to_load.append(jit_lib)
         except KeyError:
             pass
 
         # Create a context
-        self.context = LLVMContext_JIT(libs_to_load, self.ir_arch)
+        self.context = LLVMContext_JIT(libs_to_load, self.lifter)
 
         # Set the optimisation level
         self.context.optimise_level()
 
         # Save the current architecture parameters
-        self.arch = self.ir_arch.arch
+        self.arch = self.lifter.arch
 
         # Get the correspondence between registers and vmcpu struct
-        mod_name = "miasm.jitter.arch.JitCore_%s" % (self.ir_arch.arch.name)
+        mod_name = "miasm.jitter.arch.JitCore_%s" % (self.lifter.arch.name)
         mod = importlib.import_module(mod_name)
         self.context.set_vmcpu(mod.get_gpreg_offset_all())
 
@@ -140,5 +140,5 @@ class JitCore_LLVM(jitcore.JitCore):
 
         # Store a pointer on the function jitted code
         loc_key = block.loc_key
-        offset = self.ir_arch.loc_db.get_location_offset(loc_key)
+        offset = self.lifter.loc_db.get_location_offset(loc_key)
         self.offset_to_jitted_func[offset] = ptr
diff --git a/miasm/jitter/jitcore_python.py b/miasm/jitter/jitcore_python.py
index e1e905f3..269df973 100644
--- a/miasm/jitter/jitcore_python.py
+++ b/miasm/jitter/jitcore_python.py
@@ -16,16 +16,16 @@ class JitCore_Python(jitcore.JitCore):
 
     SymbExecClass = EmulatedSymbExec
 
-    def __init__(self, ir_arch, bin_stream):
-        super(JitCore_Python, self).__init__(ir_arch, bin_stream)
-        self.ir_arch = ir_arch
-        self.ircfg = self.ir_arch.new_ircfg()
+    def __init__(self, lifter, bin_stream):
+        super(JitCore_Python, self).__init__(lifter, bin_stream)
+        self.lifter = lifter
+        self.ircfg = self.lifter.new_ircfg()
 
         # CPU & VM (None for now) will be set later
 
         self.symbexec = self.SymbExecClass(
             None, None,
-            self.ir_arch, {},
+            self.lifter, {},
             sb_expr_simp=expr_simp_explicit
         )
         self.symbexec.enable_emulated_simplifications()
@@ -40,7 +40,7 @@ class JitCore_Python(jitcore.JitCore):
 
     def arch_specific(self):
         """Return arch specific information for the current architecture"""
-        arch = self.ir_arch.arch
+        arch = self.lifter.arch
         has_delayslot = False
         if arch.name == "mips32":
             from miasm.arch.mips32.jit import mipsCGen
@@ -52,7 +52,7 @@ class JitCore_Python(jitcore.JitCore):
         else:
             from miasm.jitter.codegen import CGen
             cgen_class = CGen
-        return cgen_class(self.ir_arch), has_delayslot
+        return cgen_class(self.lifter), has_delayslot
 
     def add_block(self, asmblock):
         """Create a python function corresponding to an AsmBlock
@@ -64,7 +64,7 @@ class JitCore_Python(jitcore.JitCore):
         irblocks_list = codegen.block2assignblks(asmblock)
         instr_offsets = [line.offset for line in asmblock.lines]
 
-        loc_db = self.ir_arch.loc_db
+        loc_db = self.lifter.loc_db
         local_loc_keys = []
         for irblocks in irblocks_list:
             for irblock in irblocks:
@@ -87,7 +87,7 @@ class JitCore_Python(jitcore.JitCore):
             cur_loc_key = asmblock.loc_key
 
             # Update PC helper
-            update_pc = lambda value: setattr(cpu, self.ir_arch.pc.name, value)
+            update_pc = lambda value: setattr(cpu, self.lifter.pc.name, value)
 
             while True:
                 # Retrieve the expected irblock
@@ -107,8 +107,8 @@ class JitCore_Python(jitcore.JitCore):
                 irblock_attributes = irblocks_attributes[index]
 
                 # Do IRBlock
-                new_irblock = self.ir_arch.irbloc_fix_regs_for_mode(
-                    irblock, self.ir_arch.attrib
+                new_irblock = self.lifter.irbloc_fix_regs_for_mode(
+                    irblock, self.lifter.attrib
                 )
                 if index == 0:
                     # Pre code
@@ -148,7 +148,7 @@ class JitCore_Python(jitcore.JitCore):
                             update_pc(instr.offset)
                             return instr.offset
 
-                dst = exec_engine.eval_expr(self.ir_arch.IRDst)
+                dst = exec_engine.eval_expr(self.lifter.IRDst)
                 if dst.is_int():
                     loc_key = loc_db.get_or_create_offset_location(int(dst))
                     dst = ExprLoc(loc_key, dst.size)
@@ -163,7 +163,7 @@ class JitCore_Python(jitcore.JitCore):
 
                 if instr_attrib.log_regs:
                     update_pc(offset)
-                    cpu.dump_gpregs_with_attrib(self.ir_arch.attrib)
+                    cpu.dump_gpregs_with_attrib(self.lifter.attrib)
 
                 # Post-instr checks
                 if instr_attrib.mem_read | instr_attrib.mem_write:
diff --git a/miasm/jitter/jitload.py b/miasm/jitter/jitload.py
index 20d795e6..6f3af033 100644
--- a/miasm/jitter/jitload.py
+++ b/miasm/jitter/jitload.py
@@ -179,18 +179,18 @@ class Jitter(object):
 
     C_Gen = CGen
 
-    def __init__(self, ir_arch, jit_type="gcc"):
+    def __init__(self, lifter, jit_type="gcc"):
         """Init an instance of jitter.
-        @ir_arch: ir instance for this architecture
+        @lifter: Lifter instance for this architecture
         @jit_type: JiT backend to use. Available options are:
             - "gcc"
             - "llvm"
             - "python"
         """
 
-        self.arch = ir_arch.arch
-        self.attrib = ir_arch.attrib
-        arch_name = ir_arch.arch.name  # (ir_arch.arch.name, ir_arch.attrib)
+        self.arch = lifter.arch
+        self.attrib = lifter.attrib
+        arch_name = lifter.arch.name  # (lifter.arch.name, lifter.attrib)
 
         try:
             if arch_name == "x86":
@@ -199,7 +199,7 @@ class Jitter(object):
                 from miasm.jitter.arch import JitCore_arm as jcore
             elif arch_name == "armt":
                 from miasm.jitter.arch import JitCore_arm as jcore
-                ir_arch.arch.name = 'arm'
+                lifter.arch.name = 'arm'
             elif arch_name == "aarch64":
                 from miasm.jitter.arch import JitCore_aarch64 as jcore
             elif arch_name == "msp430":
@@ -217,12 +217,12 @@ class Jitter(object):
 
         self.vm = VmMngr.Vm()
         self.cpu = jcore.JitCpu()
-        self.ir_arch = ir_arch
+        self.lifter = lifter
         self.bs = bin_stream_vm(self.vm)
-        self.ircfg = self.ir_arch.new_ircfg()
+        self.ircfg = self.lifter.new_ircfg()
 
         self.symbexec = EmulatedSymbExec(
-            self.cpu, self.vm, self.ir_arch, {}
+            self.cpu, self.vm, self.lifter, {}
         )
         self.symbexec.reset_regs()
 
@@ -238,9 +238,9 @@ class Jitter(object):
         except ImportError:
             raise RuntimeError('Unsupported jitter: %s' % jit_type)
 
-        self.jit = JitCore(self.ir_arch, self.bs)
+        self.jit = JitCore(self.lifter, self.bs)
         if isinstance(self.jit, JitCore_Cc_Base):
-            self.jit.init_codegen(self.C_Gen(self.ir_arch))
+            self.jit.init_codegen(self.C_Gen(self.lifter))
         elif jit_type == "python":
             self.jit.set_cpu_vm(self.cpu, self.vm)
 
@@ -498,7 +498,7 @@ class Jitter(object):
             log.debug('%r', fname)
             raise ValueError('unknown api', hex(jitter.pc), repr(fname))
         ret = func(jitter)
-        jitter.pc = getattr(jitter.cpu, jitter.ir_arch.pc.name)
+        jitter.pc = getattr(jitter.cpu, jitter.lifter.pc.name)
 
         # Don't break on a None return
         if ret is None:
diff --git a/miasm/os_dep/linux_stdlib.py b/miasm/os_dep/linux_stdlib.py
index 348ef9b4..f0c708ba 100644
--- a/miasm/os_dep/linux_stdlib.py
+++ b/miasm/os_dep/linux_stdlib.py
@@ -74,7 +74,7 @@ def xxx___libc_start_main(jitter):
 
         main = args.main
         # done by __libc_init_first
-        size = jitter.ir_arch.pc.size // 8
+        size = jitter.lifter.pc.size // 8
         argc = args.argc
         argv = args.ubp_av
         envp = argv + (args.argc + 1) * size
diff --git a/test/arch/x86/unit/mn_cdq.py b/test/arch/x86/unit/mn_cdq.py
index d015ede9..039cbd34 100644
--- a/test/arch/x86/unit/mn_cdq.py
+++ b/test/arch/x86/unit/mn_cdq.py
@@ -10,7 +10,7 @@ class Test_CBW_16(Asm_Test_16):
     MYSTRING = "test CBW 16"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -31,7 +31,7 @@ class Test_CBW_16_signed(Asm_Test_16):
     MYSTRING = "test CBW 16 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654381
@@ -52,7 +52,7 @@ class Test_CBW_32(Asm_Test_32):
     MYSTRING = "test CBW 32"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -73,7 +73,7 @@ class Test_CBW_32_signed(Asm_Test_32):
     MYSTRING = "test CBW 32 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654381
@@ -94,7 +94,7 @@ class Test_CDQ_32(Asm_Test_32):
     MYSTRING = "test cdq 32"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x77654321
@@ -115,7 +115,7 @@ class Test_CDQ_32_signed(Asm_Test_32):
     MYSTRING = "test cdq 32 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -136,7 +136,7 @@ class Test_CDQ_64(Asm_Test_64):
     MYSTRING = "test cdq 64"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567877654321
@@ -157,7 +157,7 @@ class Test_CDQ_64_signed(Asm_Test_64):
     MYSTRING = "test cdq 64 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887654321
@@ -178,7 +178,7 @@ class Test_CDQE_64(Asm_Test_64):
     MYSTRING = "test cdq 64"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567877654321
@@ -199,7 +199,7 @@ class Test_CDQE_64_signed(Asm_Test_64):
     MYSTRING = "test cdq 64 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887654321
@@ -220,7 +220,7 @@ class Test_CWD_32(Asm_Test_32):
     MYSTRING = "test cdq 32"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -241,7 +241,7 @@ class Test_CWD_32_signed(Asm_Test_32):
     MYSTRING = "test cdq 32"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87658321
@@ -262,7 +262,7 @@ class Test_CWD_32(Asm_Test_32):
     MYSTRING = "test cdq 32"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -283,7 +283,7 @@ class Test_CWDE_32(Asm_Test_32):
     MYSTRING = "test cwde 32"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.EAX = 0x87654321
@@ -304,7 +304,7 @@ class Test_CWDE_32_signed(Asm_Test_32):
     MYSTRING = "test cwde 32 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x87658321
@@ -325,7 +325,7 @@ class Test_CWDE_64(Asm_Test_64):
     MYSTRING = "test cwde 64"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887654321
@@ -346,7 +346,7 @@ class Test_CWDE_64_signed(Asm_Test_64):
     MYSTRING = "test cwde 64 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887658321
@@ -367,7 +367,7 @@ class Test_CQO_64(Asm_Test_64):
     MYSTRING = "test cwde 64"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x1234567887654321
@@ -388,7 +388,7 @@ class Test_CQO_64_signed(Asm_Test_64):
     MYSTRING = "test cwde 64 signed"
 
     def prepare(self):
-        self.myjit.ir_arch.loc_db.add_location("lbl_ret", self.ret_addr)
+        self.myjit.lifter.loc_db.add_location("lbl_ret", self.ret_addr)
 
     def test_init(self):
         self.myjit.cpu.RAX = 0x8234567887658321
diff --git a/test/arch/x86/unit/mn_strings.py b/test/arch/x86/unit/mn_strings.py
index 8ca148e5..1a728220 100755
--- a/test/arch/x86/unit/mn_strings.py
+++ b/test/arch/x86/unit/mn_strings.py
@@ -21,8 +21,8 @@ class Test_SCAS(Asm_Test_32):
 
     def check(self):
         assert(self.myjit.cpu.ECX == len(self.MYSTRING))
-        mystr = self.myjit.ir_arch.loc_db.get_name_location('mystr')
-        assert(self.myjit.cpu.EDI == self.myjit.ir_arch.loc_db.get_location_offset(mystr) + len(self.MYSTRING)+1)
+        mystr = self.myjit.lifter.loc_db.get_name_location('mystr')
+        assert(self.myjit.cpu.EDI == self.myjit.lifter.loc_db.get_location_offset(mystr) + len(self.MYSTRING)+1)
 
 
 class Test_MOVS(Asm_Test_32):
@@ -43,10 +43,10 @@ class Test_MOVS(Asm_Test_32):
 
     def check(self):
         assert(self.myjit.cpu.ECX == 0)
-        buffer = self.myjit.ir_arch.loc_db.get_name_location('buffer')
-        assert(self.myjit.cpu.EDI == self.myjit.ir_arch.loc_db.get_location_offset(buffer) + len(self.MYSTRING))
-        mystr = self.myjit.ir_arch.loc_db.get_name_location('mystr')
-        assert(self.myjit.cpu.ESI == self.myjit.ir_arch.loc_db.get_location_offset(mystr) + len(self.MYSTRING))
+        buffer = self.myjit.lifter.loc_db.get_name_location('buffer')
+        assert(self.myjit.cpu.EDI == self.myjit.lifter.loc_db.get_location_offset(buffer) + len(self.MYSTRING))
+        mystr = self.myjit.lifter.loc_db.get_name_location('mystr')
+        assert(self.myjit.cpu.ESI == self.myjit.lifter.loc_db.get_location_offset(mystr) + len(self.MYSTRING))
 
 
 if __name__ == "__main__":