ir: move float declaration by arch; clean ir2c

9 files changed, 125 insertions, 65 deletions

diff --git a/example/asm_x86.py b/example/asm_x86.py
index fc165da4..3e0ab1bb 100644
--- a/example/asm_x86.py
+++ b/example/asm_x86.py
@@ -30,6 +30,14 @@ main:
   CALL toto
 toto:
   POP  EDI
+
+  PUSH 0
+  FLD1
+  FLD1
+  FADD ST, ST(1)
+  FIST  DWORD PTR [ESP]
+  POP  EAX
+
   MOV  ESP, EBP
   POP  EBP
   RET
diff --git a/miasm2/arch/arm/regs.py b/miasm2/arch/arm/regs.py
index 29b2c805..2b31da38 100644
--- a/miasm2/arch/arm/regs.py
+++ b/miasm2/arch/arm/regs.py
@@ -84,3 +84,5 @@ all_regs_ids_init = [R0_init, R1_init, R2_init, R3_init,
 regs_init = {}
 for i, r in enumerate(all_regs_ids):
     regs_init[r] = all_regs_ids_init[i]
+
+regs_flt_expr = []
diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py
index c87a6412..4999ea51 100644
--- a/miasm2/arch/mips32/regs.py
+++ b/miasm2/arch/mips32/regs.py
@@ -46,7 +46,7 @@ cpr0_str[152] = "WATCHHI"
 regs_cpr0_expr, regs_cpr0_init, regs_cpr0_info = gen_regs(cpr0_str, globals())
 
 gpregs_expr, gpregs_init, gpregs = gen_regs(regs32_str, globals())
-regs_flt_expr, regs_flt_init, fltregs = gen_regs(regs_flt_str, globals())
+regs_flt_expr, regs_flt_init, fltregs = gen_regs(regs_flt_str, globals(), sz=64)
 regs_fcc_expr, regs_fcc_init, fccregs = gen_regs(regs_fcc_str, globals())
 
 
diff --git a/miasm2/arch/msp430/regs.py b/miasm2/arch/msp430/regs.py
index ea86e1fc..60638f26 100644
--- a/miasm2/arch/msp430/regs.py
+++ b/miasm2/arch/msp430/regs.py
@@ -105,3 +105,5 @@ all_regs_ids_init = [PC_init, SP_init, SR_init, R3_init,
 regs_init = {}
 for i, r in enumerate(all_regs_ids):
     regs_init[r] = all_regs_ids_init[i]
+
+regs_flt_expr = []
diff --git a/miasm2/arch/sh4/regs.py b/miasm2/arch/sh4/regs.py
index 6ffe9691..cfbca187 100644
--- a/miasm2/arch/sh4/regs.py
+++ b/miasm2/arch/sh4/regs.py
@@ -80,3 +80,5 @@ regs_init = {}
 for i, r in enumerate(all_regs_ids):
     all_regs_ids_init[i].is_term = True
     regs_init[r] = all_regs_ids_init[i]
+
+regs_flt_expr = []
diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index a2d5c062..31ee2eb9 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -55,7 +55,16 @@ replace_regs64 = {
 
     IP: RIP[:16], EIP: RIP[:32],
 
-    float_st0: ExprId("ST(0)", 64),
+    ExprId("ST", 64): float_st0,
+    ExprId("ST(0)", 64): float_st0,
+    ExprId("ST(1)", 64): float_st1,
+    ExprId("ST(2)", 64): float_st2,
+    ExprId("ST(3)", 64): float_st3,
+    ExprId("ST(4)", 64): float_st4,
+    ExprId("ST(5)", 64): float_st5,
+    ExprId("ST(6)", 64): float_st6,
+    ExprId("ST(7)", 64): float_st7,
+
 }
 
 replace_regs32 = {
@@ -67,7 +76,17 @@ replace_regs32 = {
 
     IP: EIP[:16],
 
-    float_st0: ExprId("ST(0)", 64),
+
+    ExprId("ST", 64): float_st0,
+    ExprId("ST(0)", 64): float_st0,
+    ExprId("ST(1)", 64): float_st1,
+    ExprId("ST(2)", 64): float_st2,
+    ExprId("ST(3)", 64): float_st3,
+    ExprId("ST(4)", 64): float_st4,
+    ExprId("ST(5)", 64): float_st5,
+    ExprId("ST(6)", 64): float_st6,
+    ExprId("ST(7)", 64): float_st7,
+
 }
 
 replace_regs16 = {
@@ -77,7 +96,17 @@ replace_regs16 = {
     AX: AX[:16],  CX: CX[:16],  DX: DX[:16],  BX: BX[:16],
     SP: SP[:16],  BP: BP[:16],  SI: SI[:16],  DI: DI[:16],
 
-    float_st0: ExprId("ST(0)", 64),
+
+    ExprId("ST", 64): float_st0,
+    ExprId("ST(0)", 64): float_st0,
+    ExprId("ST(1)", 64): float_st1,
+    ExprId("ST(2)", 64): float_st2,
+    ExprId("ST(3)", 64): float_st3,
+    ExprId("ST(4)", 64): float_st4,
+    ExprId("ST(5)", 64): float_st5,
+    ExprId("ST(6)", 64): float_st6,
+    ExprId("ST(7)", 64): float_st7,
+
 }
 
 replace_regs = {16: replace_regs16,
diff --git a/miasm2/arch/x86/regs.py b/miasm2/arch/x86/regs.py
index a4383249..3fc53545 100644
--- a/miasm2/arch/x86/regs.py
+++ b/miasm2/arch/x86/regs.py
@@ -248,15 +248,6 @@ reg_float_address = 'reg_float_address'
 reg_float_ds = 'reg_float_ds'
 
 
-reg_float_st0 = 'float_st0'
-reg_float_st1 = 'float_st1'
-reg_float_st2 = 'float_st2'
-reg_float_st3 = 'float_st3'
-reg_float_st4 = 'float_st4'
-reg_float_st5 = 'float_st5'
-reg_float_st6 = 'float_st6'
-reg_float_st7 = 'float_st7'
-
 
 dr0 = ExprId(reg_dr0)
 dr1 = ExprId(reg_dr1)
@@ -342,14 +333,14 @@ float_cs = ExprId(reg_float_cs, size=16)
 float_address = ExprId(reg_float_address)
 float_ds = ExprId(reg_float_ds, size=16)
 
-float_st0 = ExprId("ST", 64)
-float_st1 = ExprId("ST(1)", 64)
-float_st2 = ExprId("ST(2)", 64)
-float_st3 = ExprId("ST(3)", 64)
-float_st4 = ExprId("ST(4)", 64)
-float_st5 = ExprId("ST(5)", 64)
-float_st6 = ExprId("ST(6)", 64)
-float_st7 = ExprId("ST(7)", 64)
+float_st0 = ExprId("float_st0", 64)
+float_st1 = ExprId("float_st1", 64)
+float_st2 = ExprId("float_st2", 64)
+float_st3 = ExprId("float_st3", 64)
+float_st4 = ExprId("float_st4", 64)
+float_st5 = ExprId("float_st5", 64)
+float_st6 = ExprId("float_st6", 64)
+float_st7 = ExprId("float_st7", 64)
 
 EAX_init = ExprId('EAX_init')
 EBX_init = ExprId('EBX_init')
@@ -428,6 +419,9 @@ for i, r in enumerate(all_regs_ids):
     all_regs_ids_init[i].is_term = True
     regs_init[r] = all_regs_ids_init[i]
 
+regs_flt_expr = [float_st0, float_st1, float_st2, float_st3,
+                 float_st4, float_st5, float_st6, float_st7,
+             ]
 
 mRAX = {16: AX, 32: EAX, 64: RAX}
 mRBX = {16: BX, 32: EBX, 64: RBX}
diff --git a/miasm2/ir/ir2C.py b/miasm2/ir/ir2C.py
index 59901e02..76620dc8 100644
--- a/miasm2/ir/ir2C.py
+++ b/miasm2/ir/ir2C.py
@@ -183,59 +183,16 @@ for size in [8, 16, 32, 64]:
         prefetch_id.append(c)
         prefetch_id_size[size].append(c)
 
-
-reg_float_st0 = 'float_st0'
-reg_float_st1 = 'float_st1'
-reg_float_st2 = 'float_st2'
-reg_float_st3 = 'float_st3'
-reg_float_st4 = 'float_st4'
-reg_float_st5 = 'float_st5'
-reg_float_st6 = 'float_st6'
-reg_float_st7 = 'float_st7'
-
-
-float_st0 = ExprId(reg_float_st0, 64)
-float_st1 = ExprId(reg_float_st1, 64)
-float_st2 = ExprId(reg_float_st2, 64)
-float_st3 = ExprId(reg_float_st3, 64)
-float_st4 = ExprId(reg_float_st4, 64)
-float_st5 = ExprId(reg_float_st5, 64)
-float_st6 = ExprId(reg_float_st6, 64)
-float_st7 = ExprId(reg_float_st7, 64)
-
-fltregs32_str = ["ST(%d)" % i for i in xrange(8)]
-fltregs32_expr = [ExprId(x, 64) for x in fltregs32_str]
-
-
-float_id_e = [
-    float_st0,
-    float_st1,
-    float_st2,
-    float_st3,
-    float_st4,
-    float_st5,
-    float_st6,
-    float_st7,
-] + fltregs32_expr
-
-
 def init_arch_C(arch):
     arch.id2Cid = {}
     for x in arch.regs.all_regs_ids + prefetch_id:
         arch.id2Cid[x] = ExprId('vmcpu->' + str(x), x.size)
-    for i in xrange(8):
-        arch.id2Cid[ExprId('ST(%d)' % i, 64)] = ExprId(
-            'vmcpu->' + "float_st%d" % i, 64)
 
     arch.id2newCid = {}
 
     for x in arch.regs.all_regs_ids + prefetch_id:
         arch.id2newCid[x] = ExprId('vmcpu->%s_new' % x, x.size)
 
-    for i in xrange(8):
-        arch.id2newCid[ExprId('ST(%d)' % i, 64)] = ExprId(
-            'vmcpu->' + "float_st%d_new" % i, 64)
-
 
 def patch_c_id(arch, e):
     return e.replace_expr(arch.id2Cid)
@@ -418,7 +375,7 @@ def Expr2C(my_ir, l, exprs, gen_exception_code=False):
         if isinstance(dst, ExprId):
             id_to_update.append(dst)
             str_dst = patch_c_new_id(my_ir.arch, dst)
-            if dst in float_id_e:
+            if dst in my_ir.arch.regs.regs_flt_expr:
                 # dont mask float affectation
                 out.append('%s = (%s);' % (str_dst, str_src))
             else:
diff --git a/miasm2/jitter/arch/JitCore_mips32.h b/miasm2/jitter/arch/JitCore_mips32.h
index 8d516207..9a001989 100644
--- a/miasm2/jitter/arch/JitCore_mips32.h
+++ b/miasm2/jitter/arch/JitCore_mips32.h
@@ -167,6 +167,72 @@ typedef struct {
 	uint64_t pfmem64_19;
 
 
+	double F0;
+	double F1;
+	double F2;
+	double F3;
+	double F4;
+	double F5;
+	double F6;
+	double F7;
+	double F8;
+	double F9;
+	double F10;
+	double F11;
+	double F12;
+	double F13;
+	double F14;
+	double F15;
+	double F16;
+	double F17;
+	double F18;
+	double F19;
+	double F20;
+	double F21;
+	double F22;
+	double F23;
+	double F24;
+	double F25;
+	double F26;
+	double F27;
+	double F28;
+	double F29;
+	double F30;
+	double F31;
+
+	double F0_new;
+	double F1_new;
+	double F2_new;
+	double F3_new;
+	double F4_new;
+	double F5_new;
+	double F6_new;
+	double F7_new;
+	double F8_new;
+	double F9_new;
+	double F10_new;
+	double F11_new;
+	double F12_new;
+	double F13_new;
+	double F14_new;
+	double F15_new;
+	double F16_new;
+	double F17_new;
+	double F18_new;
+	double F19_new;
+	double F20_new;
+	double F21_new;
+	double F22_new;
+	double F23_new;
+	double F24_new;
+	double F25_new;
+	double F26_new;
+	double F27_new;
+	double F28_new;
+	double F29_new;
+	double F30_new;
+	double F31_new;
+
 
 }vm_cpu_t;