Archs: Introduce "all_regs_id_no_alias", a list of all main registers without their aliases

4 files changed, 25 insertions, 0 deletions

diff --git a/miasm2/arch/arm/regs.py b/miasm2/arch/arm/regs.py
index 6ddac2ef..2787605a 100644
--- a/miasm2/arch/arm/regs.py
+++ b/miasm2/arch/arm/regs.py
@@ -66,6 +66,8 @@ all_regs_ids = [
     zf, nf, of, cf
 ]
 
+all_regs_ids_no_alias = all_regs_ids
+
 all_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids])
 
 all_regs_ids_init = [R0_init, R1_init, R2_init, R3_init,
diff --git a/miasm2/arch/msp430/regs.py b/miasm2/arch/msp430/regs.py
index 7a389ae1..ea86e1fc 100644
--- a/miasm2/arch/msp430/regs.py
+++ b/miasm2/arch/msp430/regs.py
@@ -89,6 +89,8 @@ all_regs_ids = [
     cpuoff, gie, osc, scg0, scg1, res,
 ]
 
+all_regs_ids_no_alias = all_regs_ids
+
 all_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids])
 
 all_regs_ids_init = [PC_init, SP_init, SR_init, R3_init,
diff --git a/miasm2/arch/sh4/regs.py b/miasm2/arch/sh4/regs.py
index bfc61b04..6ffe9691 100644
--- a/miasm2/arch/sh4/regs.py
+++ b/miasm2/arch/sh4/regs.py
@@ -70,6 +70,8 @@ all_regs_ids = [
     PC, PR, R0, GBR, SR, VBR, SSR, SPC,
     SGR, DBR, MACH, MACL, FPUL, FR0]
 
+all_regs_ids_no_alias = all_regs_ids
+
 all_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids])
 
 all_regs_ids_init = [ExprId("%s_init" % x.name, x.size) for x in all_regs_ids]
diff --git a/miasm2/arch/x86/regs.py b/miasm2/arch/x86/regs.py
index 532b4f0c..293f81e7 100644
--- a/miasm2/arch/x86/regs.py
+++ b/miasm2/arch/x86/regs.py
@@ -384,6 +384,25 @@ all_regs_ids = [
     exception_flags,
 ] + fltregs32_expr
 
+all_regs_ids_no_alias = [
+    RAX, RBX, RCX, RDX, RSP, RBP, RIP, RSI, RDI,
+    R8, R9, R10, R11, R12, R13, R14, R15, R15,
+    zf, nf, pf, of, cf, af, df,
+    tf, i_f, iopl, nt, rf, vm, ac, vif, vip, i_d,
+    float_control, float_eip, float_cs, float_address, float_ds,
+    tsc1, tsc2,
+    ES, CS, SS, DS, FS, GS,
+    float_st0, float_st1, float_st2, float_st3,
+    float_st4, float_st5, float_st6, float_st7,
+    float_c0, float_c1, float_c2, float_c3,
+    cr0, cr3,
+    dr0, dr1, dr2, dr3, dr4, dr5, dr6, dr7,
+    float_stack_ptr,
+    mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
+
+    exception_flags,
+] + fltregs32_expr
+
 all_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids])
 
 all_regs_ids_init = [ExprId("%s_init" % x.name, x.size) for x in all_regs_ids]