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| author | serpilliere <serpilliere@users.noreply.github.com> | 2020-10-05 16:33:17 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-05 16:33:17 +0200 |
| commit | 49aace1a90a8079395e8283bb32f856d7af5d73c (patch) | |
| tree | d4a026041af80ef44e1937751af78ea43aa62891 | |
| parent | d9d131604f90bd1319558f14a4506a0a1b2b9065 (diff) | |
| parent | 99352528faa37bc0955e850351596d7d69a936de (diff) | |
| download | miasm-49aace1a90a8079395e8283bb32f856d7af5d73c.tar.gz miasm-49aace1a90a8079395e8283bb32f856d7af5d73c.zip | |
Merge pull request #1296 from serpilliere/fix_x86_64_cmovz
Fix x86 64 cmovz
| -rw-r--r-- | miasm/arch/x86/sem.py | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/miasm/arch/x86/sem.py b/miasm/arch/x86/sem.py index 6e593f51..4e1e12e1 100644 --- a/miasm/arch/x86/sem.py +++ b/miasm/arch/x86/sem.py @@ -403,11 +403,16 @@ def gen_cmov(ir, instr, cond, dst, src, mov_if): dstA, dstB = loc_do_expr, loc_skip_expr else: dstA, dstB = loc_skip_expr, loc_do_expr - e = [m2_expr.ExprAssign(dst, dst)] + e = [] + if instr.mode == 64: + # Force destination set in order to zero high bit orders + # In 64 bit: + # cmovz eax, ebx + # if zf == 0 => high part of RAX is set to zero + e = [m2_expr.ExprAssign(dst, dst)] e_do, extra_irs = mov(ir, instr, dst, src) e_do.append(m2_expr.ExprAssign(ir.IRDst, loc_skip_expr)) e.append(m2_expr.ExprAssign(ir.IRDst, m2_expr.ExprCond(cond, dstA, dstB))) - e += set_float_cs_eip(instr) return e, [IRBlock(ir.loc_db, loc_do, [AssignBlock(e_do, instr)])] |