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| author | Pierre Graux <pierre.graux@ensimag.grenoble-inp.fr> | 2016-08-31 14:09:40 +0200 |
|---|---|---|
| committer | Pierre Graux <pierre.graux@ensimag.grenoble-inp.fr> | 2016-09-01 12:28:35 +0200 |
| commit | 4c019ff2a7d53e3b8b1d74f6bdae6a7523d7871b (patch) | |
| tree | cedcef86bdc3c18b100923aa6a82201e2f9f8219 | |
| parent | 6d518de0330d3ffecffb138fd1d94b258052e0d0 (diff) | |
| download | miasm-4c019ff2a7d53e3b8b1d74f6bdae6a7523d7871b.tar.gz miasm-4c019ff2a7d53e3b8b1d74f6bdae6a7523d7871b.zip | |
Add a way to retrieve memory access right
| -rw-r--r-- | miasm2/jitter/vm_mngr_py.c | 21 | ||||
| -rw-r--r-- | test/jitter/vm_mngr.py | 26 | ||||
| -rw-r--r-- | test/test_all.py | 1 |
3 files changed, 48 insertions, 0 deletions
diff --git a/miasm2/jitter/vm_mngr_py.c b/miasm2/jitter/vm_mngr_py.c index 5aece270..891d4459 100644 --- a/miasm2/jitter/vm_mngr_py.c +++ b/miasm2/jitter/vm_mngr_py.c @@ -195,6 +195,25 @@ PyObject* vm_set_mem(VmMngr* self, PyObject* args) +PyObject* vm_get_mem_access(VmMngr* self, PyObject* args) +{ + PyObject *py_addr; + uint64_t page_addr; + struct memory_page_node * mpn; + + if (!PyArg_ParseTuple(args, "O", &py_addr)) + return NULL; + + PyGetInt(py_addr, page_addr); + + mpn = get_memory_page_from_address(&self->vm_mngr, page_addr, 1); + if (!mpn){ + PyErr_SetString(PyExc_RuntimeError, "cannot find address"); + return 0; + } + + return PyLong_FromUnsignedLongLong((uint64_t)mpn->access); +} PyObject* vm_get_mem(VmMngr* self, PyObject* args) { @@ -606,6 +625,8 @@ static PyMethodDef VmMngr_methods[] = { "X"}, {"add_code_bloc",(PyCFunction)vm_add_code_bloc, METH_VARARGS, "X"}, + {"get_mem_access", (PyCFunction)vm_get_mem_access, METH_VARARGS, + "X"}, {"get_mem", (PyCFunction)vm_get_mem, METH_VARARGS, "X"}, {"add_memory_page",(PyCFunction)vm_add_memory_page, METH_VARARGS, diff --git a/test/jitter/vm_mngr.py b/test/jitter/vm_mngr.py new file mode 100644 index 00000000..b2b7336b --- /dev/null +++ b/test/jitter/vm_mngr.py @@ -0,0 +1,26 @@ +from miasm2.jitter.csts import PAGE_READ, PAGE_WRITE +from miasm2.analysis.machine import Machine + +myjit = Machine("x86_32").jitter() + +base_addr = 0x13371337 +page_size = 0x1000 +data = "\x00" * page_size +rights = [0, PAGE_READ, PAGE_WRITE, PAGE_READ|PAGE_WRITE] +shuffled_rights = [PAGE_READ, 0, PAGE_READ|PAGE_WRITE, PAGE_WRITE] + +# Add pages +for i, access_right in enumerate(rights): + myjit.vm.add_memory_page(base_addr + i * page_size, access_right, data) + +# Check rights +for i, access_right in enumerate(rights): + assert myjit.vm.get_mem_access(base_addr + i * page_size) == access_right + +# Modify rights +for i, access_right in enumerate(shuffled_rights): + myjit.vm.set_mem_access(base_addr + i * page_size, access_right) + +# Check for modification +for i, access_right in enumerate(shuffled_rights): + assert myjit.vm.get_mem_access(base_addr + i * page_size) == access_right diff --git a/test/test_all.py b/test/test_all.py index c9401552..c3e3c1fb 100644 --- a/test/test_all.py +++ b/test/test_all.py @@ -319,6 +319,7 @@ for i, test_args in enumerate(test_args): ## Jitter for script in ["jitload.py", + "vm_mngr.py", ]: testset += RegressionTest([script], base_dir="jitter", tags=[TAGS["tcc"]]) |