Expression: REPLACE IS_OP_SEGM

/!\ API MODIFICATION: is_op_segm becomes is_mem_segm

is_op_segm: Returns True if is ExprOp and op == 'segm'
is_mem_segm: Returns True if is ExprMem and ptr is_op_segm

3 files changed, 20 insertions, 8 deletions

diff --git a/miasm2/arch/x86/arch.py b/miasm2/arch/x86/arch.py
index edbe9874..20fdc1cf 100644
--- a/miasm2/arch/x86/arch.py
+++ b/miasm2/arch/x86/arch.py
@@ -596,7 +596,7 @@ class instruction_x86(instruction):
                 prefix = ""
             sz = SIZE2MEMPREFIX[expr.size]
             segm = ""
-            if expr.is_op_segm():
+            if expr.is_mem_segm():
                 segm = "%s:" % expr.arg.args[0]
                 expr = expr.arg.args[1]
             else:
@@ -1720,10 +1720,10 @@ SIZE2XMMREG = {64:gpregs_mm,
 def parse_mem(expr, parent, w8, sx=0, xmm=0, mm=0):
     dct_expr = {}
     opmode = parent.v_opmode()
-    if expr.is_op_segm() and isinstance(expr.arg.args[0], ExprInt):
+    if expr.is_mem_segm() and expr.arg.args[0].is_int():
         return None, None, False
 
-    if expr.is_op_segm():
+    if expr.is_mem_segm():
         segm = expr.arg.args[0]
         ptr = expr.arg.args[1]
     else:
diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index f9673ff5..14ecbbe6 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -329,7 +329,7 @@ def movsx(ir, instr, dst, src):
 
 def lea(ir, instr, dst, src):
     ptr = src.arg
-    if src.is_op_segm():
+    if src.is_mem_segm():
         # Do not use segmentation here
         ptr = ptr.args[1]
 
@@ -2901,7 +2901,7 @@ def bittest_get(ir, instr, src, index):
         b_mask = {16: 4, 32: 5, 64: 6}
         b_decal = {16: 1, 32: 3, 64: 7}
         ptr = src.arg
-        segm = src.is_op_segm()
+        segm = src.is_mem_segm()
         if segm:
             ptr = ptr.args[1]
 
@@ -4457,7 +4457,7 @@ class ir_x86_16(ir):
                 instr.additional_info.g2.value]
         if my_ss is not None:
             for i, a in enumerate(args):
-                if isinstance(a, m2_expr.ExprMem) and not a.is_op_segm():
+                if a.is_mem() and not a.is_mem_segm():
                     args[i] = m2_expr.ExprMem(expraddr(instr.mode, m2_expr.ExprOp('segm', my_ss,
                                                                                   a.arg)), a.size)
 
diff --git a/miasm2/expression/expression.py b/miasm2/expression/expression.py
index ef7fa1f6..e134e503 100644
--- a/miasm2/expression/expression.py
+++ b/miasm2/expression/expression.py
@@ -377,6 +377,13 @@ class Expr(object):
     def is_compose(self):
         return False
 
+    def is_op_segm(self):
+        """Returns True if is ExprOp and op == 'segm'"""
+        return False
+
+    def is_mem_segm(self):
+        """Returns True if is ExprMem and ptr is_op_segm"""
+        return False
 
 class ExprInt(Expr):
 
@@ -817,8 +824,9 @@ class ExprMem(Expr):
         arg = self.arg.copy()
         return ExprMem(arg, size=self.size)
 
-    def is_op_segm(self):
-        return isinstance(self.__arg, ExprOp) and self.__arg.op == 'segm'
+    def is_mem_segm(self):
+        """Returns True if is ExprMem and ptr is_op_segm"""
+        return self.__arg.is_op_segm()
 
     def depth(self):
         return self.__arg.depth() + 1
@@ -1002,6 +1010,10 @@ class ExprOp(Expr):
             return True
         return self.op == op
 
+    def is_op_segm(self):
+        """Returns True if is ExprOp and op == 'segm'"""
+        return self.is_op('segm')
+
 class ExprSlice(Expr):
 
     __slots__ = Expr.__slots__ + ["__arg", "__start", "__stop"]