Arch/jit: add endianess support jitters

22 files changed, 191 insertions, 101 deletions

diff --git a/example/asm_arm.py b/example/asm_arm.py
index b891ba1a..60e85259 100644
--- a/example/asm_arm.py
+++ b/example/asm_arm.py
@@ -22,11 +22,12 @@ def my_ast_id2expr(t):
 my_var_parser = parse_ast(my_ast_id2expr, my_ast_int2expr)
 base_expr.setParseAction(my_var_parser)
 
-blocs, symbol_pool = parse_asm.parse_txt(my_mn, "arm", '''
+txt = '''
 main:
   STMFD  SP!, {R4, R5, LR}
   MOV    R0, mystr & 0xffff
   ORR    R0, R0, mystr & 0xffff0000
+  MOV    R4, R0
   MOV    R1, mystrend & 0xffff
   ORR    R1, R1, mystrend & 0xffff0000
 xxx:
@@ -38,15 +39,8 @@ loop:
   STRB   R3, [R0], 1
   CMP    R0, R1
   BNE    loop
-  EOR    R0, R0, R0
-  BNE    end
-  EOR    R1, R1, R1
-  EOR    R2, R2, R2
-  EORGE  R1, R1, R1
-  EORGE  R2, R2, R2
-  ADDLTS R2, R2, R2
-  SUBEQ  R2, R2, R2
 end:
+  MOV    R0, R4
   LDMFD  SP!, {R4, R5, PC}
 key:
 .long 0x11223344
@@ -56,27 +50,36 @@ mystrend:
 .long 0
 test:
 .long mystrend - key + 0x1122
-''')
+'''
+
+blocs_b, symbol_pool_b = parse_asm.parse_txt(my_mn, "b", txt)
+blocs_l, symbol_pool_l = parse_asm.parse_txt(my_mn, "l", txt)
+
 
 # fix shellcode addr
-symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0)
+symbol_pool_b.set_offset(symbol_pool_b.getby_name("main"), 0x0)
+symbol_pool_l.set_offset(symbol_pool_l.getby_name("main"), 0x0)
 
-for b in blocs[0]:
-    print b
 # graph sc####
-g = asmbloc.bloc2graph(blocs[0])
+g = asmbloc.bloc2graph(blocs_l[0])
 open("graph.txt", "w").write(g)
 
-s = StrPatchwork()
+s_b = StrPatchwork()
+s_l = StrPatchwork()
 
 print "symbols"
-print symbol_pool
+print symbol_pool_l
 # dont erase from start to shell code padading
-resolved_b, patches = asmbloc.asm_resolve_final(
-    my_mn, blocs[0], symbol_pool)
-print patches
+resolved_b, patches_b = asmbloc.asm_resolve_final(
+    my_mn, blocs_b[0], symbol_pool_b)
+resolved_l, patches_l = asmbloc.asm_resolve_final(
+    my_mn, blocs_l[0], symbol_pool_l)
+print patches_b
 
-for offset, raw in patches.items():
-    s[offset] = raw
+for offset, raw in patches_b.items():
+    s_b[offset] = raw
+for offset, raw in patches_l.items():
+    s_l[offset] = raw
 
-open('demo_arm.bin', 'wb').write(str(s))
+open('demo_arm_b.bin', 'w').write(str(s_b))
+open('demo_arm_l.bin', 'w').write(str(s_l))
diff --git a/example/asm_arm_sc.py b/example/asm_arm_sc.py
index 71f2d716..16bfa181 100644
--- a/example/asm_arm_sc.py
+++ b/example/asm_arm_sc.py
@@ -27,7 +27,7 @@ base_expr.setParseAction(my_var_parser)
 
 st = StrPatchwork()
 
-blocs, symbol_pool = parse_asm.parse_txt(mn_arm, 'arm', '''
+blocs, symbol_pool = parse_asm.parse_txt(mn_arm, 'l', '''
 main:
     MOV R1, R0
     MOV R2, 0x100
diff --git a/example/asm_armt.py b/example/asm_armt.py
index c95c4bac..1c810e5b 100644
--- a/example/asm_armt.py
+++ b/example/asm_armt.py
@@ -23,7 +23,7 @@ def my_ast_id2expr(t):
 my_var_parser = parse_ast(my_ast_id2expr, my_ast_int2expr)
 base_expr.setParseAction(my_var_parser)
 
-blocs, symbol_pool = parse_asm.parse_txt(my_mn, "armt", '''
+txt = '''
 memcpy:
      PUSH    {R0-R3, LR}
      B       test_end
@@ -51,29 +51,38 @@ main:
 
 mystr:
 .string "toto"
-''')
+'''
+
+blocs_b, symbol_pool_b = parse_asm.parse_txt(my_mn, "b", txt)
+blocs_l, symbol_pool_l = parse_asm.parse_txt(my_mn, "l", txt)
 
 # fix shellcode addr
-symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x3a4b8)
+symbol_pool_b.set_offset(symbol_pool_b.getby_name("main"), 0)
+symbol_pool_l.set_offset(symbol_pool_l.getby_name("main"), 0)
 
-for b in blocs[0]:
-    print b
 # graph sc####
-g = asmbloc.bloc2graph(blocs[0])
+g = asmbloc.bloc2graph(blocs_b[0])
 open("graph.txt", "w").write(g)
 
-s = StrPatchwork()
+s_b = StrPatchwork()
+s_l = StrPatchwork()
 
 print "symbols"
-print symbol_pool
+print symbol_pool_b
 # dont erase from start to shell code padading
-resolved_b, patches = asmbloc.asm_resolve_final(
-    my_mn, blocs[0], symbol_pool)
-print patches
+resolved_b, patches_b = asmbloc.asm_resolve_final(
+    my_mn, blocs_b[0], symbol_pool_b)
+resolved__l, patches_l = asmbloc.asm_resolve_final(
+    my_mn, blocs_l[0], symbol_pool_l)
+print patches_b
+print patches_l
 
 
 
-for offset, raw in patches.items():
-    s[offset] = raw
+for offset, raw in patches_b.items():
+    s_b[offset] = raw
+for offset, raw in patches_l.items():
+    s_l[offset] = raw
 
-open('demo_armt.bin', 'wb').write(str(s))
+open('demo_armt_b.bin', 'wb').write(str(s_b))
+open('demo_armt_l.bin', 'wb').write(str(s_l))
diff --git a/example/expression/asm_to_ir.py b/example/expression/asm_to_ir.py
index b5fe0ec5..cec32c06 100644
--- a/example/expression/asm_to_ir.py
+++ b/example/expression/asm_to_ir.py
@@ -39,7 +39,7 @@ for b in blocs:
 
 print "symbols:"
 print symbol_pool
-resolved_b, patches = asmbloc.asm_resolve_final(mn_x86, 32, blocs, symbol_pool)
+resolved_b, patches = asmbloc.asm_resolve_final(mn_x86, blocs, symbol_pool)
 
 # Translate to IR
 ir_arch = ir_a_x86_32(symbol_pool)
diff --git a/example/test_jit_arm.py b/example/test_jit_arm.py
index da4a0e6d..997fa4ff 100644
--- a/example/test_jit_arm.py
+++ b/example/test_jit_arm.py
@@ -32,3 +32,4 @@ if options.address is None:
 
 sb.run()
 
+
diff --git a/example/test_jit_mips32.py b/example/test_jit_mips32.py
index 42188ab8..a4f23319 100644
--- a/example/test_jit_mips32.py
+++ b/example/test_jit_mips32.py
@@ -10,7 +10,7 @@ from pdb import pm
 
 parser = ArgumentParser(
     description="""Sandbox raw binary with mips32 engine
-(ex: test_jit_mips32.py example/mips32_sc.bin 0)""")
+(ex: test_jit_mips32.py example/mips32_sc_l.bin 0)""")
 parser.add_argument("-r", "--log-regs",
                     help="Log registers value for each instruction",
                     action="store_true")
diff --git a/miasm2/analysis/machine.py b/miasm2/analysis/machine.py
index bf433554..3f88b759 100644
--- a/miasm2/analysis/machine.py
+++ b/miasm2/analysis/machine.py
@@ -24,15 +24,24 @@ class Machine(object):
         gdbserver = None
 
         # Import on runtime for performance issue
-        if machine_name == "arm":
-            from miasm2.arch.arm.disasm import dis_arm as dis_engine
+        if machine_name == "arml":
+            from miasm2.arch.arm.disasm import dis_arml as dis_engine
             from miasm2.arch.arm.arch import mn_arm as mn
-            from miasm2.arch.arm.ira import ir_a_arm as ira
-            from miasm2.arch.arm.jit import jitter_arm as jitter
-        elif machine_name == "armt":
-            from miasm2.arch.arm.disasm import dis_armt as dis_engine
+            from miasm2.arch.arm.ira import ir_a_arml as ira
+            from miasm2.arch.arm.jit import jitter_arml as jitter
+        elif machine_name == "armb":
+            from miasm2.arch.arm.disasm import dis_armb as dis_engine
+            from miasm2.arch.arm.arch import mn_arm as mn
+            from miasm2.arch.arm.ira import ir_a_armb as ira
+            from miasm2.arch.arm.jit import jitter_armb as jitter
+        elif machine_name == "armtl":
+            from miasm2.arch.arm.disasm import dis_armtl as dis_engine
+            from miasm2.arch.arm.arch import mn_armt as mn
+            from miasm2.arch.arm.ira import ir_a_armtl as ira
+        elif machine_name == "armtb":
+            from miasm2.arch.arm.disasm import dis_armtb as dis_engine
             from miasm2.arch.arm.arch import mn_armt as mn
-            from miasm2.arch.arm.ira import ir_a_armt as ira
+            from miasm2.arch.arm.ira import ir_a_armtb as ira
         elif machine_name == "sh4":
             from miasm2.arch.sh4.disasm import dis_sha4 as dis_engine
             from miasm2.arch.sh4.arch import mn_sh4 as mn
@@ -62,13 +71,13 @@ class Machine(object):
         elif machine_name == "mips32b":
             from miasm2.arch.mips32.disasm import dis_mips32b as dis_engine
             from miasm2.arch.mips32.arch import mn_mips32 as mn
-            from miasm2.arch.mips32.ira import ir_a_mips32 as ira
-            #from miasm2.arch.mips32.jit import jitter_mips32 as jitter
+            from miasm2.arch.mips32.ira import ir_a_mips32b as ira
+            from miasm2.arch.mips32.jit import jitter_mips32b as jitter
         elif machine_name == "mips32l":
             from miasm2.arch.mips32.disasm import dis_mips32l as dis_engine
             from miasm2.arch.mips32.arch import mn_mips32 as mn
-            from miasm2.arch.mips32.ira import ir_a_mips32 as ira
-            from miasm2.arch.mips32.jit import jitter_mips32 as jitter
+            from miasm2.arch.mips32.ira import ir_a_mips32l as ira
+            from miasm2.arch.mips32.jit import jitter_mips32l as jitter
         else:
             raise ValueError('Unknown machine: %s' % machine_name)
 
diff --git a/miasm2/analysis/sandbox.py b/miasm2/analysis/sandbox.py
index 8a1e1ca4..6ee108e4 100644
--- a/miasm2/analysis/sandbox.py
+++ b/miasm2/analysis/sandbox.py
@@ -246,7 +246,7 @@ class Arch_x86_32(Arch):
 
 
 class Arch_arml(Arch):
-    _ARCH_ = "arm"
+    _ARCH_ = "arml"
     STACK_SIZE = 0x100000
 
     def __init__(self):
diff --git a/miasm2/arch/arm/disasm.py b/miasm2/arch/arm/disasm.py
index 64e10eec..3ba08995 100644
--- a/miasm2/arch/arm/disasm.py
+++ b/miasm2/arch/arm/disasm.py
@@ -36,16 +36,24 @@ def cb_arm_disasm(mn, attrib, pool_bin, cur_bloc, offsets_to_dis, symbol_pool):
         func(mn, attrib, pool_bin, cur_bloc, offsets_to_dis, symbol_pool)
 
 
-class dis_arm(disasmEngine):
-    attrib = 'arm'
-
+class dis_armb(disasmEngine):
+    attrib = 'b'
     def __init__(self, bs=None, **kwargs):
-        super(dis_arm, self).__init__(mn_arm, self.attrib, bs, **kwargs)
+        super(dis_armb, self).__init__(mn_arm, self.attrib, bs, **kwargs)
         self.dis_bloc_callback = cb_arm_disasm
 
+class dis_arml(disasmEngine):
+    attrib = 'l'
+    def __init__(self, bs=None, **kwargs):
+        super(dis_arml, self).__init__(mn_arm, self.attrib, bs, **kwargs)
+        self.dis_bloc_callback = cb_arm_disasm
 
-class dis_armt(disasmEngine):
-    attrib = 'armt'
+class dis_armtb(disasmEngine):
+    attrib = 'b'
+    def __init__(self, bs=None, **kwargs):
+        super(dis_armtb, self).__init__(mn_armt, self.attrib, bs, **kwargs)
 
+class dis_armtl(disasmEngine):
+    attrib = 'l'
     def __init__(self, bs=None, **kwargs):
-        super(dis_armt, self).__init__(mn_armt, self.attrib, bs, **kwargs)
+        super(dis_armtl, self).__init__(mn_armt, self.attrib, bs, **kwargs)
diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py
index b92800e7..8cfe2da0 100644
--- a/miasm2/arch/arm/ira.py
+++ b/miasm2/arch/arm/ira.py
@@ -4,22 +4,26 @@
 from miasm2.expression.expression import *
 from miasm2.ir.ir import ir, irbloc
 from miasm2.ir.analysis import ira
-from miasm2.arch.arm.sem import ir_arm, ir_armt
+from miasm2.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb
 from miasm2.arch.arm.regs import *
 # from miasm2.core.graph import DiGraph
 
 
-class ir_a_arm_base(ir_arm, ira):
+class ir_a_arml_base(ir_arml, ira):
+    def __init__(self, symbol_pool=None):
+        ir_arml.__init__(self, symbol_pool)
+        self.ret_reg = self.arch.regs.R0
 
+class ir_a_armb_base(ir_armb, ira):
     def __init__(self, symbol_pool=None):
-        ir_arm.__init__(self, symbol_pool)
+        ir_armb.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.R0
 
 
-class ir_a_arm(ir_a_arm_base):
+class ir_a_arml(ir_a_arml_base):
 
     def __init__(self, symbol_pool=None):
-        ir_a_arm_base.__init__(self, symbol_pool)
+        ir_a_arml_base.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.R0
 
     # for test XXX TODO
@@ -120,9 +124,19 @@ class ir_a_arm(ir_a_arm_base):
     def sizeof_pointer(self):
         return 32
 
+class ir_a_armb(ir_a_armb_base, ir_a_arml):
+
+    def __init__(self, symbol_pool=None):
+        ir_a_armb_base.__init__(self, symbol_pool)
+        self.ret_reg = self.arch.regs.R0
+
 
-class ir_a_armt(ir_armt, ir_a_arm):
+class ir_a_armtl(ir_armtl, ir_a_arml):
+    def __init__(self, symbol_pool):
+        ir_armtl.__init__(self, symbol_pool)
+        self.ret_reg = self.arch.regs.R0
 
+class ir_a_armtb(ir_a_armtl, ir_armtb, ir_a_armb):
     def __init__(self, symbol_pool):
-        ir_armt.__init__(self, symbol_pool)
+        ir_armtb.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.R0
diff --git a/miasm2/arch/arm/jit.py b/miasm2/arch/arm/jit.py
index 2947674a..29b701df 100644
--- a/miasm2/arch/arm/jit.py
+++ b/miasm2/arch/arm/jit.py
@@ -1,7 +1,7 @@
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
 from miasm2.core.utils import *
-from miasm2.arch.arm.sem import ir_arm
+from miasm2.arch.arm.sem import ir_arml
 
 import logging
 
@@ -11,11 +11,12 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
-class jitter_arm(jitter):
+class jitter_arml(jitter):
 
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
-        jitter.__init__(self, ir_arm(sp), *args, **kwargs)
+        jitter.__init__(self, ir_arml(sp), *args, **kwargs)
+        self.vm.set_little_endian()
         self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
 
     def push_uint32_t(self, v):
@@ -87,3 +88,8 @@ class jitter_arm(jitter):
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
+
+class jitter_armb(jitter_arml):
+    def __init__(self, *args, **kwargs):
+        jitter_arml.__init__(self)
+        self.vm.set_big_endian()
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 72625eab..e0e59555 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -1116,10 +1116,9 @@ class arminfo:
     # offset
 
 
-class ir_arm(ir):
-
+class ir_arml(ir):
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_arm, "arm", symbol_pool)
+        ir.__init__(self, mn_arm, "l", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 32)
@@ -1152,10 +1151,16 @@ class ir_arm(ir):
         return instr_ir, extra_ir
 
 
-class ir_armt(ir):
+class ir_armb(ir_arml):
+    def __init__(self, symbol_pool=None):
+        ir.__init__(self, mn_arm, "b", symbol_pool)
+        self.pc = PC
+        self.sp = SP
+        self.IRDst = ExprId('IRDst', 32)
 
+class ir_armtl(ir):
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_armt, "armt", symbol_pool)
+        ir.__init__(self, mn_armt, "l", symbol_pool)
         self.pc = PC
         self.sp = SP
         self.IRDst = ExprId('IRDst', 32)
@@ -1163,3 +1168,10 @@ class ir_armt(ir):
     def get_ir(self, instr):
         return get_mnemo_expr(self, instr, *instr.args)
 
+class ir_armtb(ir_armtl):
+    def __init__(self, symbol_pool=None):
+        ir.__init__(self, mn_armt, "b", symbol_pool)
+        self.pc = PC
+        self.sp = SP
+        self.IRDst = ExprId('IRDst', 32)
+
diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py
index cb084411..c070b4ba 100644
--- a/miasm2/arch/mips32/ira.py
+++ b/miasm2/arch/mips32/ira.py
@@ -4,13 +4,13 @@
 from miasm2.expression.expression import *
 from miasm2.ir.ir import ir, irbloc
 from miasm2.ir.analysis import ira
-from miasm2.arch.mips32.sem import ir_mips32
+from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
 from miasm2.arch.mips32.regs import *
 from miasm2.core.asmbloc import expr_is_int_or_label, expr_is_label
-class ir_a_mips32(ir_mips32, ira):
 
+class ir_a_mips32l(ir_mips32l, ira):
     def __init__(self, symbol_pool=None):
-        ir_mips32.__init__(self, symbol_pool)
+        ir_mips32l.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.V0
 
 
@@ -79,3 +79,9 @@ class ir_a_mips32(ir_mips32, ira):
     def sizeof_pointer(self):
         return 32
 
+
+
+class ir_a_mips32b(ir_mips32b, ir_a_mips32l):
+    def __init__(self, symbol_pool=None):
+        ir_mips32b.__init__(self, symbol_pool)
+        self.ret_reg = self.arch.regs.V0
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
index 61fa8a5a..93223896 100644
--- a/miasm2/arch/mips32/jit.py
+++ b/miasm2/arch/mips32/jit.py
@@ -1,7 +1,7 @@
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
 from miasm2.core.utils import *
-from miasm2.arch.mips32.sem import ir_mips32
+from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
 
 import logging
 
@@ -11,13 +11,13 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
-class jitter_mips32(jitter):
+class jitter_mips32l(jitter):
 
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
-        jitter.__init__(self, ir_mips32(sp), *args, **kwargs)
+        jitter.__init__(self, ir_mips32l(sp), *args, **kwargs)
+        self.vm.set_little_endian()
         self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
-        self.ir_arch.attrib = 'l'
 
     def push_uint32_t(self, v):
         self.cpu.SP -= 4
@@ -35,3 +35,11 @@ class jitter_mips32(jitter):
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
+
+
+class jitter_mips32b(jitter_mips32l):
+    def __init__(self, *args, **kwargs):
+        sp = asmbloc.asm_symbol_pool()
+        jitter.__init__(self, ir_mips32b(sp), *args, **kwargs)
+        self.vm.set_big_endian()
+        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
diff --git a/miasm2/arch/mips32/sem.py b/miasm2/arch/mips32/sem.py
index 365444d7..57263478 100644
--- a/miasm2/arch/mips32/sem.py
+++ b/miasm2/arch/mips32/sem.py
@@ -522,10 +522,10 @@ def get_mnemo_expr(ir, instr, *args):
     instr, extra_ir = mnemo_func[instr.name.lower()](ir, instr, *args)
     return instr, extra_ir
 
-class ir_mips32(ir):
+class ir_mips32l(ir):
 
     def __init__(self, symbol_pool=None):
-        ir.__init__(self, mn_mips32, None, symbol_pool)
+        ir.__init__(self, mn_mips32, 'l', symbol_pool)
         self.pc = mn_mips32.getpc()
         self.sp = mn_mips32.getsp()
         self.IRDst = ExprId('IRDst', 32)
@@ -590,3 +590,10 @@ class ir_mips32(ir):
         self.post_add_bloc(bloc, ir_blocs_all)
         return ir_blocs_all
     """
+
+class ir_mips32b(ir_mips32l):
+    def __init__(self, symbol_pool=None):
+        ir.__init__(self, mn_mips32, 'b', symbol_pool)
+        self.pc = mn_mips32.getpc()
+        self.sp = mn_mips32.getsp()
+        self.IRDst = ExprId('IRDst', 32)
diff --git a/miasm2/arch/msp430/jit.py b/miasm2/arch/msp430/jit.py
index 008a3036..5a4ff58b 100644
--- a/miasm2/arch/msp430/jit.py
+++ b/miasm2/arch/msp430/jit.py
@@ -1,7 +1,6 @@
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
 from miasm2.core.utils import *
-from miasm2.arch.arm.sem import ir_arm
 
 import logging
 
@@ -17,6 +16,7 @@ class jitter_msp430(jitter):
         from miasm2.arch.msp430.sem import ir_msp430
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_msp430(sp), *args, **kwargs)
+        self.vm.set_little_endian()
         self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
 
     def push_uint16_t(self, v):
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py
index b1d70f9b..556f70cb 100644
--- a/miasm2/arch/x86/jit.py
+++ b/miasm2/arch/x86/jit.py
@@ -17,6 +17,7 @@ class jitter_x86_16(jitter):
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_x86_16(sp), *args, **kwargs)
+        self.vm.set_little_endian()
         self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP
         self.ir_arch.do_stk_segm = False
         self.orig_irbloc_fix_regs_for_mode = self.ir_arch.irbloc_fix_regs_for_mode
@@ -48,6 +49,7 @@ class jitter_x86_32(jitter):
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_x86_32(sp), *args, **kwargs)
+        self.vm.set_little_endian()
         self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP
         self.ir_arch.do_stk_segm = False
 
@@ -139,6 +141,7 @@ class jitter_x86_64(jitter):
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
         jitter.__init__(self, ir_x86_64(sp), *args, **kwargs)
+        self.vm.set_little_endian()
         self.ir_arch.jit_pc = self.ir_arch.arch.regs.RIP
         self.ir_arch.do_stk_segm = False
 
diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py
index 63217352..a66ba4cf 100644
--- a/test/arch/arm/arch.py
+++ b/test/arch/arm/arch.py
@@ -26,7 +26,7 @@ if 0:
 
 if 0:
     import cProfile
-    cProfile.run('mn_arm.dis("\xe1\xa0\xa0\x06", mode_arm)')
+    cProfile.run('mn_arm.dis("\xe1\xa0\xa0\x06", "l")')
     # l = mn_arm.dis(bin_stream("\xe1\xa0\xa0\x06"), mode_arm)
     # print l
     """
@@ -240,14 +240,14 @@ for s, l in reg_tests_arm:
     print "-" * 80
     s = s[12:]
     b = h2i((l))
-    mn = mn_arm.dis(b, mode_arm)
+    mn = mn_arm.dis(b, 'l')
     print [str(x) for x in mn.args]
     print s
     print mn
     assert(str(mn) == s)
     # print hex(b)
     # print [str(x.get()) for x in mn.args]
-    l = mn_arm.fromstring(s, mode_arm)
+    l = mn_arm.fromstring(s, 'l')
     # print l
     assert(str(l) == s)
     a = mn_arm.asm(l)
@@ -467,14 +467,14 @@ for s, l in reg_tests_armt:
     s = s[12:]
     b = h2i((l))
     print b.encode('hex')
-    mn = mn_armt.dis(b, mode_armthumb)
+    mn = mn_armt.dis(b, 'l')
     print [str(x) for x in mn.args]
     print s
     print mn
     assert(str(mn) == s)
     # print hex(b)
     # print [str(x.get()) for x in mn.args]
-    l = mn_armt.fromstring(s, mode_armthumb)
+    l = mn_armt.fromstring(s, 'l')
     # print l
     assert(str(l) == s)
     a = mn_armt.asm(l)
@@ -496,7 +496,7 @@ parse_tests = [
 
 for l in parse_tests:
     print "-"*80
-    l = mn_arm.fromstring(l, mode_arm)
+    l = mn_arm.fromstring(l, 'l')
     print l.name, ", ".join([str(a) for a in l.args])
 """
 
@@ -517,7 +517,7 @@ off = 0
 instr_num = 0
 ts = time.time()
 while off < bs.getlen():
-    mn = mn_arm.dis(bs, mode_arm, off)
+    mn = mn_arm.dis(bs, 'l', off)
     instr_num += 1
     off += 4
 print 'instr per sec:', instr_num / (time.time() - ts)
@@ -537,11 +537,11 @@ off = 0
 instr_num = 0
 ts = time.time()
 while off < bs.getlen():
-    mn = mn_armt.dis(bs, mode_armthumb, off)
+    mn = mn_armt.dis(bs, 'l', off)
     # print instr_num, off, str(mn)
     instr_num += 1
     off += mn.l
 print 'instr per sec:', instr_num / (time.time() - ts)
 
 import cProfile
-cProfile.run(r'mn_arm.dis("\xe1\xa0\xa0\x06", mode_arm)')
+cProfile.run(r'mn_arm.dis("\xe1\xa0\xa0\x06", "l")')
diff --git a/test/arch/arm/sem.py b/test/arch/arm/sem.py
index a84a9499..a9f3eb1d 100644
--- a/test/arch/arm/sem.py
+++ b/test/arch/arm/sem.py
@@ -5,8 +5,8 @@ import unittest
 import logging
 
 from miasm2.ir.symbexec import symbexec
-from miasm2.arch.arm.arch import mn_arm as mn, mode_arm as mode
-from miasm2.arch.arm.sem import ir_arm as ir_arch
+from miasm2.arch.arm.arch import mn_arm as mn
+from miasm2.arch.arm.sem import ir_arml as ir_arch
 from miasm2.arch.arm.regs import *
 from miasm2.expression.expression import *
 
@@ -23,9 +23,9 @@ def compute(asm, inputstate={}, debug=False):
     sympool.update({k: ExprInt_from(k, v) for k, v in inputstate.iteritems()})
     interm = ir_arch()
     symexec = symbexec(interm, sympool)
-    instr = mn.fromstring(asm, mode)
+    instr = mn.fromstring(asm, "l")
     code = mn.asm(instr)[0]
-    instr = mn.dis(code, mode)
+    instr = mn.dis(code, "l")
     instr.offset = inputstate.get(PC, 0)
     interm.add_instr(instr)
     symexec.emul_ir_blocs(interm, instr.offset)
diff --git a/test/arch/x86/sem.py b/test/arch/x86/sem.py
index bd28bd45..de2d14f3 100644
--- a/test/arch/x86/sem.py
+++ b/test/arch/x86/sem.py
@@ -48,7 +48,7 @@ def compute_txt(ir, mode, txt, inputstate={}, debug=False):
     blocs, symbol_pool = parse_asm.parse_txt(mn, mode, txt)
     symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0)
     resolved_b, patches = asmbloc.asm_resolve_final(
-        mn, str(mode), blocs[0], symbol_pool)
+        mn, blocs[0], symbol_pool)
     interm = ir(symbol_pool)
     for bbl in resolved_b:
         interm.add_bloc(bbl[0])
diff --git a/test/arch/x86/unit/asm_test.py b/test/arch/x86/unit/asm_test.py
index 8310134d..f28c4d2f 100644
--- a/test/arch/x86/unit/asm_test.py
+++ b/test/arch/x86/unit/asm_test.py
@@ -54,7 +54,7 @@ class Asm_Test(object):
         symbol_pool.set_offset(symbol_pool.getby_name("main"), 0x0)
         s = StrPatchwork()
         resolved_b, patches = asmbloc.asm_resolve_final(
-            mn_x86, '32', blocs[0], symbol_pool)
+            mn_x86, blocs[0], symbol_pool)
         for offset, raw in patches.items():
             s[offset] = raw
 
diff --git a/test/test_all.py b/test/test_all.py
index 4264927b..23e45246 100644
--- a/test/test_all.py
+++ b/test/test_all.py
@@ -85,11 +85,15 @@ all_tests = {
             ["expression/asm_to_ir.py"],
             ["expression/expr_grapher.py"],
             ["expression/simplification_add.py"],
-            ["test_dis.py", "-g", "-s", "-m", "arm", "demo_arm.bin", "0"],
+            ["test_dis.py", "-g", "-s", "-m", "arml", "demo_arm_l.bin", "0"],
+            ["test_dis.py", "-g", "-s", "-m", "armb", "demo_arm_b.bin", "0"],
+            ["test_dis.py", "-g", "-s", "-m", "armtl", "demo_armt_l.bin", "0"],
+            ["test_dis.py", "-g", "-s", "-m", "armtb", "demo_armt_b.bin", "0"],
             ["test_dis.py", "-g", "-s", "-m",
                 "x86_32", "box_x86_32.bin", "0x401000"],
             ["test_dis.py", "-g", "-s", "-m", "msp430", "msp430_sc.bin", "0"],
-            ["test_dis.py", "-g", "-s", "-m", "mips32l", "mips32_sc.bin", "0"],
+            ["test_dis.py", "-g", "-s", "-m", "mips32l", "mips32_sc_l.bin", "0"],
+            ["test_dis.py", "-g", "-s", "-m", "mips32b", "mips32_sc_b.bin", "0"],
             ["expression/solve_condition_stp.py",
                 "expression/simple_test.bin"],
         ],
@@ -99,7 +103,7 @@ all_tests = {
                     ["test_jit_x86_32.py", "x86_32_sc.bin"],
                     ["test_jit_arm.py", "md5_arm", "-a", "A684"],
                     ["test_jit_msp430.py", "msp430_sc.bin", "0"],
-                    ["test_jit_mips32.py", "mips32_sc.bin", "0"],
+                    ["test_jit_mips32.py", "mips32_sc_l.bin", "0"],
                     ["sandbox_pe_x86_32.py", "box_x86_32.bin"],
                     ["sandbox_pe_x86_32.py", "box_x86_32_enc.bin"],
                     ["sandbox_pe_x86_32.py", "box_x86_32_mod.bin"],