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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-09 15:56:50 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-09 15:59:17 +0100 |
| commit | 7cb92935ff1bae9d100275134704f5ff477c46c8 (patch) | |
| tree | 474fc7bad703281000cbad629faea7268b0d19e9 | |
| parent | 400fce77dcff990537966e2849630da482e9817e (diff) | |
| download | miasm-7cb92935ff1bae9d100275134704f5ff477c46c8.tar.gz miasm-7cb92935ff1bae9d100275134704f5ff477c46c8.zip | |
Aarch64: add svc
| -rw-r--r-- | miasm2/arch/aarch64/sem.py | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index 57f4a658..697fa981 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -3,7 +3,7 @@ from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock from miasm2.arch.aarch64.arch import mn_aarch64, conds_expr, replace_regs from miasm2.arch.aarch64.regs import * from miasm2.core.sembuilder import SemBuilder -from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO +from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO, EXCEPT_INT_XX # CPSR: N Z C V @@ -150,6 +150,7 @@ ctx = {"PC": PC, "exception_flags": exception_flags, "interrupt_num": interrupt_num, "EXCEPT_DIV_BY_ZERO": EXCEPT_DIV_BY_ZERO, + "EXCEPT_INT_XX": EXCEPT_INT_XX, } sbuild = SemBuilder(ctx) @@ -721,6 +722,12 @@ def extr(arg1, arg2, arg3, arg4): compose = m2_expr.ExprCompose(arg2, arg3) arg1 = compose[int(arg4.arg):int(arg4)+arg1.size] + +@sbuild.parse +def svc(arg1): + exception_flags = m2_expr.ExprInt(EXCEPT_INT_XX, exception_flags.size) + interrupt_num = m2_expr.ExprInt(int(arg1), interrupt_num.size) + mnemo_func = sbuild.functions mnemo_func.update({ 'and': and_l, |