Arm arch: add sxtb/sxth (tx to t.pourcelot)

2 files changed, 22 insertions, 0 deletions

diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index dd0cf665..348820db 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -1470,6 +1470,9 @@ armop("qadd",
 
 armop("uxtb", [bs('01101110'), bs('1111'), rd, rot_rm, bs('00'), bs('0111'), rm_noarg])
 armop("uxth", [bs('01101111'), bs('1111'), rd, rot_rm, bs('00'), bs('0111'), rm_noarg])
+armop("sxtb", [bs('01101010'), bs('1111'), rd, rot_rm, bs('00'), bs('0111'), rm_noarg])
+armop("sxth", [bs('01101011'), bs('1111'), rd, rot_rm, bs('00'), bs('0111'), rm_noarg])
+
 
 class arm_widthm1(arm_imm, m_arg):
     def decode(self, v):
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py
index 07db3cfb..9608c1f0 100644
--- a/miasm2/arch/arm/sem.py
+++ b/miasm2/arch/arm/sem.py
@@ -826,6 +826,23 @@ def uxth(ir, instr, a, b):
         dst = PC
     return dst, e
 
+def sxtb(ir, instr, a, b):
+    e = []
+    e.append(ExprAff(a, b[:8].signExtend(32)))
+    dst = None
+    if PC in a.get_r():
+        dst = PC
+    return dst, e
+
+def sxth(ir, instr, a, b):
+    e = []
+    e.append(ExprAff(a, b[:16].signExtend(32)))
+    dst = None
+    if PC in a.get_r():
+        dst = PC
+    return dst, e
+
+
 def ubfx(ir, instr, a, b, c, d):
     e = []
     c = int(c.arg)
@@ -966,6 +983,8 @@ mnemo_condm0 = {'add': add,
                 'ldsh': ldrsh,
                 'uxtb': uxtb,
                 'uxth': uxth,
+                'sxtb': sxtb,
+                'sxth': sxth,
                 'ubfx': ubfx,
                 }