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| author | serpilliere <devnull@localhost> | 2014-06-30 10:34:59 +0200 |
|---|---|---|
| committer | serpilliere <devnull@localhost> | 2014-06-30 10:34:59 +0200 |
| commit | abbd24f74235d715c0aaaaf7cf56916691e652a8 (patch) | |
| tree | 40ae6ea22b4a1956280314de9e02821230dbe2b8 | |
| parent | b22dcfbca8ee132d5a9fe46d7050330afe68af16 (diff) | |
| download | miasm-abbd24f74235d715c0aaaaf7cf56916691e652a8.tar.gz miasm-abbd24f74235d715c0aaaaf7cf56916691e652a8.zip | |
arm: Fix thumb ldr pc offset (tx t.pourcelot)
| -rw-r--r-- | miasm2/arch/arm/arch.py | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index b169d608..d8a1faeb 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -781,7 +781,7 @@ class arm_imm8_12(m_arg): self.parent.updown.value = 0 v = -v & 0xFFFFFFFF if v & 0x3: - log.debug('arg shoulb be 4 aligned') + log.debug('arg should be 4 aligned') return False v >>= 2 self.value = v @@ -1516,6 +1516,12 @@ class arm_offreg(m_arg): class arm_offpc(arm_offreg): off_reg = regs_expr[15] + def decodeval(self, v): + return v << 2 + + def encodeval(self, v): + return v >> 2 + class arm_offsp(arm_offreg): @@ -1905,7 +1911,7 @@ armtop("b", [bs('11100'), offs11]) armtop("und", [bs('1101'), bs('1110'), imm8_d1]) # -# thumnb2 ###################### +# thumb2 ###################### # # ARM Architecture Reference Manual Thumb-2 Supplement |