Merge pull request #882 from w4kfu/revert-879-mov_assignexpr_rot_shift

Revert 879 mov assignexpr rot shift ; Simplify assignexpr rot shift & patch simplification

2 files changed, 7 insertions, 14 deletions

diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py
index 565f7571..c0b578f6 100644
--- a/miasm2/arch/x86/sem.py
+++ b/miasm2/arch/x86/sem.py
@@ -636,9 +636,7 @@ def _rotate_tpl(ir, instr, dst, src, op, left=False):
             m2_expr.ExprAssign(of, new_of),
             m2_expr.ExprAssign(dst, res)
             ]
-    e = []
-    if dst.size == 32 and dst in replace_regs[64]:
-        e.append(m2_expr.ExprAssign(dst[:dst.size], dst))
+    e = [m2_expr.ExprAssign(dst, dst)]
     # Don't generate conditional shifter on constant
     if isinstance(shifter, m2_expr.ExprInt):
         if int(shifter) != 0:
@@ -686,9 +684,7 @@ def rotate_with_carry_tpl(ir, instr, op, dst, src):
             m2_expr.ExprAssign(of, new_of),
             m2_expr.ExprAssign(dst, new_dst)
             ]
-    e = []
-    if dst.size == 32 and dst in replace_regs[64]:
-        e.append(m2_expr.ExprAssign(dst[:dst.size], dst))
+    e = [m2_expr.ExprAssign(dst, dst)]
     # Don't generate conditional shifter on constant
     if isinstance(shifter, m2_expr.ExprInt):
         if int(shifter) != 0:
@@ -774,9 +770,7 @@ def _shift_tpl(op, ir, instr, a, b, c=None, op_inv=None, left=False,
         m2_expr.ExprAssign(a, res),
     ]
     e_do += update_flag_znp(res)
-    e = []
-    if a.size == 32 and a in replace_regs[64]:
-        e.append(m2_expr.ExprAssign(a[:a.size], a))
+    e = [m2_expr.ExprAssign(a, a)]
     # Don't generate conditional shifter on constant
     if isinstance(shifter, m2_expr.ExprInt):
         if int(shifter) != 0:
@@ -5652,7 +5646,6 @@ class ir_x86_16(IntermediateRepresentation):
 
         instr_ir, extra_ir = mnemo_func[
             instr.name.lower()](self, instr, *args)
-
         self.mod_pc(instr, instr_ir, extra_ir)
         instr.additional_info.except_on_instr = False
         if instr.additional_info.g1.value & 6 == 0 or \
diff --git a/miasm2/jitter/codegen.py b/miasm2/jitter/codegen.py
index 6c0e7a9b..e8177ab5 100644
--- a/miasm2/jitter/codegen.py
+++ b/miasm2/jitter/codegen.py
@@ -170,7 +170,8 @@ class CGen(object):
             # Simplify high level operators
             out = []
             for irblock in irblocks:
-                new_irblock = irblock.simplify(expr_simp_high_to_explicit)[1]
+                new_irblock = self.ir_arch.irbloc_fix_regs_for_mode(irblock, self.ir_arch.attrib)
+                new_irblock = new_irblock.simplify(expr_simp_high_to_explicit)[1]
                 out.append(new_irblock)
             irblocks = out
 
@@ -631,13 +632,12 @@ class CGen(object):
         for instr, irblocks in zip(block.lines, irblocks_list):
             instr_attrib, irblocks_attributes = self.get_attributes(instr, irblocks, log_mn, log_regs)
             for index, irblock in enumerate(irblocks):
-                new_irblock = self.ir_arch.irbloc_fix_regs_for_mode(irblock, self.ir_arch.attrib)
-                label = str(new_irblock.loc_key)
+                label = str(irblock.loc_key)
                 out.append("%-40s // %.16X %s" %
                            (label + ":", instr.offset, instr))
                 if index == 0:
                     out += self.gen_pre_code(instr_attrib)
-                out += self.gen_irblock(instr_attrib, irblocks_attributes[index], instr_offsets, new_irblock)
+                out += self.gen_irblock(instr_attrib, irblocks_attributes[index], instr_offsets, irblock)
 
         out += self.gen_finalize(block)