Arch/Mips32: Remove wildcard imports

2 files changed, 235 insertions, 193 deletions

diff --git a/miasm2/arch/mips32/arch.py b/miasm2/arch/mips32/arch.py
index cbcd5e79..50dc1c86 100644
--- a/miasm2/arch/mips32/arch.py
+++ b/miasm2/arch/mips32/arch.py
@@ -2,13 +2,14 @@
 #-*- coding:utf-8 -*-
 
 import logging
-from pyparsing import *
-from miasm2.expression.expression import *
-from miasm2.core.cpu import *
 from collections import defaultdict
+
+from pyparsing import Literal, Group, Optional
+
+from miasm2.expression.expression import ExprMem, ExprInt, ExprInt32, ExprId
 from miasm2.core.bin_stream import bin_stream
-import miasm2.arch.mips32.regs as regs_module
-from miasm2.arch.mips32.regs import *
+import miasm2.arch.mips32.regs as regs
+import miasm2.core.cpu as cpu
 
 
 log = logging.getLogger("mips32dis")
@@ -18,7 +19,7 @@ log.addHandler(console_handler)
 log.setLevel(logging.DEBUG)
 
 
-gpregs = reg_info(regs32_str, regs32_expr)
+gpregs = cpu.reg_info(regs.regs32_str, regs.regs32_expr)
 
 
 
@@ -38,12 +39,12 @@ def deref2expr_nooff(s, l, t):
         raise NotImplementedError("TODO")
     return ExprMem(t[1])
 
-my_var_parser = parse_ast(ast_id2expr, ast_int2expr)
-base_expr.setParseAction(my_var_parser)
-
+base_expr = cpu.base_expr
 
-deref_off = Group(Optional(base_expr) + LPARENTHESIS + gpregs.parser + RPARENTHESIS).setParseAction(deref2expr)
-deref_nooff = Group(LPARENTHESIS + gpregs.parser + RPARENTHESIS).setParseAction(deref2expr_nooff)
+deref_off = Group(Optional(cpu.base_expr) + LPARENTHESIS + gpregs.parser + \
+                      RPARENTHESIS).setParseAction(deref2expr)
+deref_nooff = Group(LPARENTHESIS + gpregs.parser + \
+                        RPARENTHESIS).setParseAction(deref2expr_nooff)
 deref = deref_off | deref_nooff
 
 
@@ -56,7 +57,7 @@ br_1 = ['BGEZ', 'BLTZ', 'BGTZ', 'BLEZ', 'BC1T', 'BC1F']
 br_2 = ['BEQ', 'BEQL', 'BNE']
 
 
-class instruction_mips32(instruction):
+class instruction_mips32(cpu.instruction):
     delayslot = 1
 
     def __init__(self, *args, **kargs):
@@ -155,7 +156,7 @@ class instruction_mips32(instruction):
         e = self.args[ndx]
         print 'FIX', ndx, e, self.offset, self.l
         if self.offset is None:
-            raise ValueError('symbol not resolved %s' % l)
+            raise ValueError('symbol not resolved %s' % self.l)
         if not isinstance(e, ExprInt):
             return
         off = e.arg - (self.offset + self.l)
@@ -171,42 +172,42 @@ class instruction_mips32(instruction):
         return args
 
 
-class mn_mips32(cls_mn):
+class mn_mips32(cpu.cls_mn):
     delayslot = 0
     name = "mips32"
-    regs = regs_module
+    regs = regs
     bintree = {}
     num = 0
     all_mn = []
     all_mn_mode = defaultdict(list)
     all_mn_name = defaultdict(list)
     all_mn_inst = defaultdict(list)
-    pc = {'l':PC, 'b':PC}
-    sp = {'l':SP, 'b':SP}
+    pc = {'l':regs.PC, 'b':regs.PC}
+    sp = {'l':regs.SP, 'b':regs.SP}
     instruction = instruction_mips32
     max_instruction_len = 4
 
     @classmethod
     def getpc(cls, attrib = None):
-        return PC
+        return regs.PC
 
     @classmethod
     def getsp(cls, attrib = None):
-        return SP
+        return regs.SP
 
     def additional_info(self):
         info = additional_info()
         return info
 
     @classmethod
-    def getbits(cls, bs, attrib, start, n):
+    def getbits(cls, bitstream, attrib, start, n):
         if not n:
             return 0
         o = 0
         while n:
             offset = start / 8
             n_offset = cls.endian_offset(attrib, offset)
-            c = cls.getbytes(bs, n_offset, 1)
+            c = cls.getbytes(bitstream, n_offset, 1)
             if not c:
                 raise IOError
             c = ord(c)
@@ -263,7 +264,7 @@ def mips32op(name, fields, args=None, alias=False):
     #type(name, (mn_mips32b,), dct)
 
 
-class mips32_reg(reg_noarg, m_arg):
+class mips32_reg(cpu.reg_noarg, cpu.m_arg):
     pass
 
 class mips32_gpreg(mips32_reg):
@@ -271,22 +272,22 @@ class mips32_gpreg(mips32_reg):
     parser = reg_info.parser
 
 class mips32_fltpreg(mips32_reg):
-    reg_info = fltregs
+    reg_info = regs.fltregs
     parser = reg_info.parser
 
 
 class mips32_fccreg(mips32_reg):
-    reg_info = fccregs
+    reg_info = regs.fccregs
     parser = reg_info.parser
 
-class mips32_imm(imm_noarg):
-    parser = base_expr
+class mips32_imm(cpu.imm_noarg):
+    parser = cpu.base_expr
 
 
 class mips32_s16imm_noarg(mips32_imm):
     def decode(self, v):
         v = v & self.lmask
-        v = sign_ext(v, 16, 32)
+        v = cpu.sign_ext(v, 16, 32)
         self.expr = ExprInt32(v)
         return True
 
@@ -296,7 +297,7 @@ class mips32_s16imm_noarg(mips32_imm):
         v = self.expr.arg.arg
         if v & 0x80000000:
             nv = v & ((1 << 16) - 1)
-            assert( v == sign_ext(nv, 16, 32))
+            assert( v == cpu.sign_ext(nv, 16, 32))
             v = nv
         self.value = v
         return True
@@ -305,7 +306,7 @@ class mips32_soff_noarg(mips32_imm):
     def decode(self, v):
         v = v & self.lmask
         v <<= 2
-        v = sign_ext(v, 16+2, 32)
+        v = cpu.sign_ext(v, 16+2, 32)
         self.expr = ExprInt32(v)
         return True
 
@@ -315,20 +316,20 @@ class mips32_soff_noarg(mips32_imm):
         v = self.expr.arg.arg
         if v & 0x80000000:
             nv = v & ((1 << 16+2) - 1)
-            assert( v == sign_ext(nv, 16+2, 32))
+            assert( v == cpu.sign_ext(nv, 16+2, 32))
             v = nv
         self.value = v>>2
         return True
 
 
-class mips32_s16imm(mips32_s16imm_noarg, m_arg):
+class mips32_s16imm(mips32_s16imm_noarg, cpu.m_arg):
     pass
 
-class mips32_soff(mips32_soff_noarg, m_arg):
+class mips32_soff(mips32_soff_noarg, cpu.m_arg):
     pass
 
 
-class mips32_instr_index(mips32_imm, m_arg):
+class mips32_instr_index(mips32_imm, cpu.m_arg):
     def decode(self, v):
         v = v & self.lmask
         self.expr = ExprInt32(v<<2)
@@ -347,7 +348,7 @@ class mips32_instr_index(mips32_imm, m_arg):
         return True
 
 
-class mips32_u16imm(mips32_imm, m_arg):
+class mips32_u16imm(mips32_imm, cpu.m_arg):
     def decode(self, v):
         v = v & self.lmask
         self.expr = ExprInt32(v)
@@ -361,7 +362,7 @@ class mips32_u16imm(mips32_imm, m_arg):
         self.value = v
         return True
 
-class mips32_dreg_imm(m_arg):
+class mips32_dreg_imm(cpu.m_arg):
     parser = deref
     def decode(self, v):
         imm = self.parent.imm.expr
@@ -394,7 +395,7 @@ class mips32_dreg_imm(m_arg):
         assert(len(arg.args) == 2 and arg.op == '+')
         return "%s(%s)"%(arg.args[1], arg.args[0])
 
-class mips32_esize(mips32_imm, m_arg):
+class mips32_esize(mips32_imm, cpu.m_arg):
     def decode(self, v):
         v = v & self.lmask
         self.expr = ExprInt32(v+1)
@@ -408,7 +409,7 @@ class mips32_esize(mips32_imm, m_arg):
         self.value = v
         return True
 
-class mips32_eposh(mips32_imm, m_arg):
+class mips32_eposh(mips32_imm, cpu.m_arg):
     def decode(self, v):
         self.expr = ExprInt32(v-int(self.parent.epos.expr.arg)+1)
         return True
@@ -425,60 +426,61 @@ class mips32_imm(mips32_imm):
     pass
 
 
-class mips32_cpr(m_arg):
-    parser = regs_cpr0_info.parser
+class mips32_cpr(cpu.m_arg):
+    parser = regs.regs_cpr0_info.parser
     def decode(self, v):
         index = int(self.parent.cpr0.expr.arg) << 3
         index += v
-        self.expr = regs_cpr0_expr[index]
+        self.expr = regs.regs_cpr0_expr[index]
         return True
     def encode(self):
         e = self.expr
-        if not e in regs_cpr0_expr:
+        if not e in regs.regs_cpr0_expr:
             return False
-        index = regs_cpr0_expr.index(e)
+        index = regs.regs_cpr0_expr.index(e)
         self.value = index & 7
         index >>=2
         self.parent.cpr0.value = index
         return True
 
-rs = bs(l=5, cls=(mips32_gpreg,))
-rt = bs(l=5, cls=(mips32_gpreg,))
-rd = bs(l=5, cls=(mips32_gpreg,))
-ft = bs(l=5, cls=(mips32_fltpreg,))
-fs = bs(l=5, cls=(mips32_fltpreg,))
-fd = bs(l=5, cls=(mips32_fltpreg,))
+rs = cpu.bs(l=5, cls=(mips32_gpreg,))
+rt = cpu.bs(l=5, cls=(mips32_gpreg,))
+rd = cpu.bs(l=5, cls=(mips32_gpreg,))
+ft = cpu.bs(l=5, cls=(mips32_fltpreg,))
+fs = cpu.bs(l=5, cls=(mips32_fltpreg,))
+fd = cpu.bs(l=5, cls=(mips32_fltpreg,))
 
-s16imm = bs(l=16, cls=(mips32_s16imm,))
-u16imm = bs(l=16, cls=(mips32_u16imm,))
-sa = bs(l=5, cls=(mips32_u16imm,))
-base = bs(l=5, cls=(mips32_dreg_imm,))
-soff = bs(l=16, cls=(mips32_soff,))
+s16imm = cpu.bs(l=16, cls=(mips32_s16imm,))
+u16imm = cpu.bs(l=16, cls=(mips32_u16imm,))
+sa = cpu.bs(l=5, cls=(mips32_u16imm,))
+base = cpu.bs(l=5, cls=(mips32_dreg_imm,))
+soff = cpu.bs(l=16, cls=(mips32_soff,))
 
-cpr0 = bs(l=5, cls=(mips32_imm,), fname="cpr0")
-cpr =  bs(l=3, cls=(mips32_cpr,))
+cpr0 = cpu.bs(l=5, cls=(mips32_imm,), fname="cpr0")
+cpr =  cpu.bs(l=3, cls=(mips32_cpr,))
 
 
-s16imm_noarg = bs(l=16, cls=(mips32_s16imm_noarg,), fname="imm",
+s16imm_noarg = cpu.bs(l=16, cls=(mips32_s16imm_noarg,), fname="imm",
                   order=-1)
 
-hint = bs(l=5, default_val="00000")
-fcc = bs(l=3, cls=(mips32_fccreg,))
+hint = cpu.bs(l=5, default_val="00000")
+fcc = cpu.bs(l=3, cls=(mips32_fccreg,))
 
-sel = bs(l=3, cls=(mips32_u16imm,))
+sel = cpu.bs(l=3, cls=(mips32_u16imm,))
 
-code = bs(l=20, cls=(mips32_u16imm,))
+code = cpu.bs(l=20, cls=(mips32_u16imm,))
 
-esize = bs(l=5, cls=(mips32_esize,))
-epos = bs(l=5, cls=(mips32_u16imm,), fname="epos",
+esize = cpu.bs(l=5, cls=(mips32_esize,))
+epos = cpu.bs(l=5, cls=(mips32_u16imm,), fname="epos",
           order=-1)
 
-eposh = bs(l=5, cls=(mips32_eposh,))
+eposh = cpu.bs(l=5, cls=(mips32_eposh,))
 
-instr_index = bs(l=26, cls=(mips32_instr_index,))
-bs_fmt = bs_mod_name(l=5, fname='fmt', mn_mod={0x10: '.S', 0x11: '.D', 0x14: '.W',
-                                               0x15: '.L', 0x16: '.PS'})
-class bs_cond(bs_mod_name):
+instr_index = cpu.bs(l=26, cls=(mips32_instr_index,))
+bs_fmt = cpu.bs_mod_name(l=5, fname='fmt', mn_mod={0x10: '.S', 0x11: '.D',
+                                                   0x14: '.W', 0x15: '.L',
+                                                   0x16: '.PS'})
+class bs_cond(cpu.bs_mod_name):
     mn_mod = ['.F', '.UN', '.EQ', '.UEQ',
               '.OLT', '.ULT', '.OLE', '.ULE',
               '.SF', '.NGLE', '.SEQ', '.NGL',
@@ -489,7 +491,7 @@ class bs_cond(bs_mod_name):
         raise NotImplementedError("Not implemented")
 
 
-class bs_cond_name(bs_divert):
+class bs_cond_name(cpu.bs_divert):
     prio = 2
     mn_mod = [['.F', '.UN', '.EQ', '.UEQ',
                '.OLT', '.ULT', '.OLE', '.ULE'],
@@ -507,10 +509,10 @@ class bs_cond_name(bs_divert):
             mm = self.mn_mod[cond1.value]
             for value, new_name in enumerate(mm):
                 nfields = fields[:]
-                s = int2bin(value, self.args['l'])
+                s = cpu.int2bin(value, self.args['l'])
                 args = dict(self.args)
                 args.update({'strbits': s})
-                f = bs(**args)
+                f = cpu.bs(**args)
                 nfields[index] = f
                 ndct = dict(dct)
                 ndct['name'] = name + new_name
@@ -519,7 +521,7 @@ class bs_cond_name(bs_divert):
 
 
 
-class bs_cond_mod(bs_mod_name):
+class bs_cond_mod(cpu.bs_mod_name):
     prio = 1
 
 bs_cond = bs_cond_mod(l=4,
@@ -530,162 +532,200 @@ bs_cond = bs_cond_mod(l=4,
 
 
 
-bs_arith = bs_name(l=6, name={'ADDU':0b100001,
-                              'SUBU':0b100011,
-                              'OR':0b100101,
-                              'AND':0b100100,
-                              'SLTU':0b101011,
-                              'XOR':0b100110,
-                              'SLT':0b101010,
-                              'SUBU':0b100011,
-                              'NOR':0b100111,
-                              'MOVN':0b001011,
-                              'MOVZ':0b001010,
-                              })
-
-bs_shift = bs_name(l=6, name={'SLL':0b000000,
-                              'SRL':0b000010,
-                              'SRA':0b000011,
-                              })
-
-bs_shift1 = bs_name(l=6, name={'SLLV':0b000100,
-                               'SRLV':0b000110,
-                               'SRAV':0b000111,
-                               })
-
-
-bs_arithfmt = bs_name(l=6, name={'ADD':0b000000,
-                                 'SUB':0b000001,
-                                 'MUL':0b000010,
-                                 'DIV':0b000011,
-                                 })
-
-bs_s_l = bs_name(l=6, name = {"SW":    0b101011,
-                              "SH":    0b101001,
-                              "SB":    0b101000,
-                              "LW":    0b100011,
-                              "LH":    0b100001,
-                              "LB":    0b100000,
-                              "LHU":   0b100101,
-                              "LBU":   0b100100,
-                              "LWL":   0b100010,
-                              "LWR":   0b100110,
-
-                              "SWL":   0b101010,
-                              "SWR":   0b101110,
-                              })
-
-
-bs_oax = bs_name(l=6, name = {"ORI":    0b001101,
-                              "ANDI":   0b001100,
-                              "XORI":   0b001110,
-                              })
-
-bs_bcc = bs_name(l=5, name = {"BGEZ":    0b00001,
-                              "BGEZL":   0b00011,
-                              "BGEZAL":  0b10001,
-                              "BGEZALL": 0b10011,
-                              "BLTZ":    0b00000,
-                              "BLTZL":   0b00010,
-                              "BLTZAL":  0b10000,
-                              "BLTZALL": 0b10010,
-                              })
-
-
-
-mips32op("addi",    [bs('001000'), rs, rt, s16imm], [rt, rs, s16imm])
-mips32op("addiu",   [bs('001001'), rs, rt, s16imm], [rt, rs, s16imm])
-mips32op("nop",     [bs('0'*32)], alias = True)
-mips32op("lui",     [bs('001111'), bs('00000'), rt, u16imm])
+bs_arith = cpu.bs_name(l=6, name={'ADDU':0b100001,
+                                  'SUBU':0b100011,
+                                  'OR':0b100101,
+                                  'AND':0b100100,
+                                  'SLTU':0b101011,
+                                  'XOR':0b100110,
+                                  'SLT':0b101010,
+                                  'SUBU':0b100011,
+                                  'NOR':0b100111,
+                                  'MOVN':0b001011,
+                                  'MOVZ':0b001010,
+                                  })
+
+bs_shift = cpu.bs_name(l=6, name={'SLL':0b000000,
+                                  'SRL':0b000010,
+                                  'SRA':0b000011,
+                                  })
+
+bs_shift1 = cpu.bs_name(l=6, name={'SLLV':0b000100,
+                                   'SRLV':0b000110,
+                                   'SRAV':0b000111,
+                                   })
+
+
+bs_arithfmt = cpu.bs_name(l=6, name={'ADD':0b000000,
+                                     'SUB':0b000001,
+                                     'MUL':0b000010,
+                                     'DIV':0b000011,
+                                     })
+
+bs_s_l = cpu.bs_name(l=6, name = {"SW":    0b101011,
+                                  "SH":    0b101001,
+                                  "SB":    0b101000,
+                                  "LW":    0b100011,
+                                  "LH":    0b100001,
+                                  "LB":    0b100000,
+                                  "LHU":   0b100101,
+                                  "LBU":   0b100100,
+                                  "LWL":   0b100010,
+                                  "LWR":   0b100110,
+
+                                  "SWL":   0b101010,
+                                  "SWR":   0b101110,
+                                  })
+
+
+bs_oax = cpu.bs_name(l=6, name = {"ORI":    0b001101,
+                                  "ANDI":   0b001100,
+                                  "XORI":   0b001110,
+                                  })
+
+bs_bcc = cpu.bs_name(l=5, name = {"BGEZ":    0b00001,
+                                  "BGEZL":   0b00011,
+                                  "BGEZAL":  0b10001,
+                                  "BGEZALL": 0b10011,
+                                  "BLTZ":    0b00000,
+                                  "BLTZL":   0b00010,
+                                  "BLTZAL":  0b10000,
+                                  "BLTZALL": 0b10010,
+                                  })
+
+
+
+mips32op("addi",    [cpu.bs('001000'), rs, rt, s16imm], [rt, rs, s16imm])
+mips32op("addiu",   [cpu.bs('001001'), rs, rt, s16imm], [rt, rs, s16imm])
+mips32op("nop",     [cpu.bs('0'*32)], alias = True)
+mips32op("lui",     [cpu.bs('001111'), cpu.bs('00000'), rt, u16imm])
 mips32op("oax",     [bs_oax, rs, rt, u16imm], [rt, rs, u16imm])
 
-mips32op("arith",   [bs('000000'), rs, rt, rd, bs('00000'), bs_arith], [rd, rs, rt])
-mips32op("shift1",  [bs('000000'), rs, rt, rd, bs('00000'), bs_shift1], [rd, rt, rs])
+mips32op("arith",   [cpu.bs('000000'), rs, rt, rd, cpu.bs('00000'), bs_arith],
+         [rd, rs, rt])
+mips32op("shift1",  [cpu.bs('000000'), rs, rt, rd, cpu.bs('00000'), bs_shift1],
+         [rd, rt, rs])
 
-mips32op("shift",   [bs('000000'), bs('00000'), rt, rd, sa, bs_shift], [rd, rt, sa])
+mips32op("shift",   [cpu.bs('000000'), cpu.bs('00000'), rt, rd, sa, bs_shift],
+         [rd, rt, sa])
 
-mips32op("rotr",    [bs('000000'), bs('00001'), rt, rd, sa, bs('000010')], [rd, rt, sa])
+mips32op("rotr",    [cpu.bs('000000'), cpu.bs('00001'), rt, rd, sa,
+                     cpu.bs('000010')], [rd, rt, sa])
 
-mips32op("mul",     [bs('011100'), rs, rt, rd, bs('00000'), bs('000010')], [rd, rs, rt])
-mips32op("div",     [bs('000000'), rs, rt, bs('0000000000'), bs('011010')])
+mips32op("mul",     [cpu.bs('011100'), rs, rt, rd, cpu.bs('00000'),
+                     cpu.bs('000010')], [rd, rs, rt])
+mips32op("div",     [cpu.bs('000000'), rs, rt, cpu.bs('0000000000'),
+                     cpu.bs('011010')])
 
 mips32op("s_l",     [bs_s_l, base, rt, s16imm_noarg], [rt, base])
 
 #mips32op("mfc0",    [bs('010000'), bs('00000'), rt, rd, bs('00000000'), sel])
-mips32op("mfc0",    [bs('010000'), bs('00000'), rt, cpr0, bs('00000000'), cpr])
-mips32op("mfc1",    [bs('010001'), bs('00000'), rt, fs, bs('00000000000')])
+mips32op("mfc0",    [cpu.bs('010000'), cpu.bs('00000'), rt, cpr0,
+                     cpu.bs('00000000'), cpr])
+mips32op("mfc1",    [cpu.bs('010001'), cpu.bs('00000'), rt, fs,
+                     cpu.bs('00000000000')])
 
-mips32op("ldc1",    [bs('110101'), base, ft, s16imm_noarg], [ft, base])
+mips32op("ldc1",    [cpu.bs('110101'), base, ft, s16imm_noarg], [ft, base])
 
-mips32op("mov",     [bs('010001'), bs_fmt, bs('00000'), fs, fd, bs('000110')], [fd, fs])
+mips32op("mov",     [cpu.bs('010001'), bs_fmt, cpu.bs('00000'), fs, fd,
+                     cpu.bs('000110')], [fd, fs])
 
-mips32op("add",     [bs('010001'), bs_fmt, ft, fs, fd, bs_arithfmt], [fd, fs, ft])
+mips32op("add",     [cpu.bs('010001'), bs_fmt, ft, fs, fd, bs_arithfmt],
+         [fd, fs, ft])
 
-mips32op("divu",    [bs('000000'), rs, rt, bs('0000000000'), bs('011011')])
-mips32op("mult",    [bs('000000'), rs, rt, bs('0000000000'), bs('011000')])
-mips32op("multu",   [bs('000000'), rs, rt, bs('0000000000'), bs('011001')])
-mips32op("mflo",    [bs('000000'), bs('0000000000'), rd, bs('00000'), bs('010010')])
-mips32op("mfhi",    [bs('000000'), bs('0000000000'), rd, bs('00000'), bs('010000')])
+mips32op("divu",    [cpu.bs('000000'), rs, rt, cpu.bs('0000000000'),
+                     cpu.bs('011011')])
+mips32op("mult",    [cpu.bs('000000'), rs, rt, cpu.bs('0000000000'),
+                     cpu.bs('011000')])
+mips32op("multu",   [cpu.bs('000000'), rs, rt, cpu.bs('0000000000'),
+                     cpu.bs('011001')])
+mips32op("mflo",    [cpu.bs('000000'), cpu.bs('0000000000'), rd,
+                     cpu.bs('00000'), cpu.bs('010010')])
+mips32op("mfhi",    [cpu.bs('000000'), cpu.bs('0000000000'), rd,
+                     cpu.bs('00000'), cpu.bs('010000')])
 
 
-mips32op("b",       [bs('000100'), bs('00000'), bs('00000'), soff], alias = True)
-mips32op("bne",     [bs('000101'), rs, rt, soff])
-mips32op("beq",     [bs('000100'), rs, rt, soff])
+mips32op("b",       [cpu.bs('000100'), cpu.bs('00000'), cpu.bs('00000'), soff],
+         alias = True)
+mips32op("bne",     [cpu.bs('000101'), rs, rt, soff])
+mips32op("beq",     [cpu.bs('000100'), rs, rt, soff])
 
-mips32op("blez",    [bs('000110'), rs, bs('00000'), soff])
+mips32op("blez",    [cpu.bs('000110'), rs, cpu.bs('00000'), soff])
 
-mips32op("bcc",     [bs('000001'), rs, bs_bcc, soff])
+mips32op("bcc",     [cpu.bs('000001'), rs, bs_bcc, soff])
 
-mips32op("bgtz",    [bs('000111'), rs, bs('00000'), soff])
-mips32op("bal",     [bs('000001'), bs('00000'), bs('10001'), soff], alias = True)
+mips32op("bgtz",    [cpu.bs('000111'), rs, cpu.bs('00000'), soff])
+mips32op("bal",     [cpu.bs('000001'), cpu.bs('00000'), cpu.bs('10001'), soff],
+         alias = True)
 
 
-mips32op("slti",    [bs('001010'), rs, rt, s16imm], [rt, rs, s16imm])
-mips32op("sltiu",   [bs('001011'), rs, rt, s16imm], [rt, rs, s16imm])
+mips32op("slti",    [cpu.bs('001010'), rs, rt, s16imm], [rt, rs, s16imm])
+mips32op("sltiu",   [cpu.bs('001011'), rs, rt, s16imm], [rt, rs, s16imm])
 
 
-mips32op("j",       [bs('000010'), instr_index])
-mips32op("jal",     [bs('000011'), instr_index])
-mips32op("jalr",    [bs('000000'), rs, bs('00000'), rd, hint, bs('001001')])
-mips32op("jr",      [bs('000000'), rs, bs('0000000000'), hint, bs('001000')])
+mips32op("j",       [cpu.bs('000010'), instr_index])
+mips32op("jal",     [cpu.bs('000011'), instr_index])
+mips32op("jalr",    [cpu.bs('000000'), rs, cpu.bs('00000'), rd, hint,
+                     cpu.bs('001001')])
+mips32op("jr",      [cpu.bs('000000'), rs, cpu.bs('0000000000'), hint,
+                     cpu.bs('001000')])
 
-mips32op("lwc1",    [bs('110001'), base, ft, s16imm_noarg], [ft, base])
+mips32op("lwc1",    [cpu.bs('110001'), base, ft, s16imm_noarg], [ft, base])
 
 #mips32op("mtc0",    [bs('010000'), bs('00100'), rt, rd, bs('00000000'), sel])
-mips32op("mtc0",    [bs('010000'), bs('00100'), rt, cpr0, bs('00000000'), cpr])
-mips32op("mtc1",    [bs('010001'), bs('00100'), rt, fs, bs('00000000000')])
+mips32op("mtc0",    [cpu.bs('010000'), cpu.bs('00100'), rt, cpr0,
+                     cpu.bs('00000000'), cpr])
+mips32op("mtc1",    [cpu.bs('010001'), cpu.bs('00100'), rt, fs,
+                     cpu.bs('00000000000')])
 
 # XXXX TODO CFC1
-mips32op("cfc1",    [bs('010001'), bs('00010'), rt, fs, bs('00000000000')])
+mips32op("cfc1",    [cpu.bs('010001'), cpu.bs('00010'), rt, fs,
+                     cpu.bs('00000000000')])
 # XXXX TODO CTC1
-mips32op("ctc1",    [bs('010001'), bs('00110'), rt, fs, bs('00000000000')])
+mips32op("ctc1",    [cpu.bs('010001'), cpu.bs('00110'), rt, fs,
+                     cpu.bs('00000000000')])
 
-mips32op("break",   [bs('000000'), code, bs('001101')])
-mips32op("syscall", [bs('000000'), code, bs('001100')])
+mips32op("break",   [cpu.bs('000000'), code, cpu.bs('001101')])
+mips32op("syscall", [cpu.bs('000000'), code, cpu.bs('001100')])
 
 
-mips32op("c",       [bs('010001'), bs_fmt, ft, fs, fcc, bs('0'), bs('0'), bs('11'), bs_cond], [fcc, fs, ft])
+mips32op("c",       [cpu.bs('010001'), bs_fmt, ft, fs, fcc, cpu.bs('0'),
+                     cpu.bs('0'), cpu.bs('11'), bs_cond], [fcc, fs, ft])
 
 
-mips32op("bc1t",    [bs('010001'), bs('01000'), fcc, bs('0'), bs('1'), soff])
-mips32op("bc1f",    [bs('010001'), bs('01000'), fcc, bs('0'), bs('0'), soff])
+mips32op("bc1t",    [cpu.bs('010001'), cpu.bs('01000'), fcc, cpu.bs('0'),
+                     cpu.bs('1'), soff])
+mips32op("bc1f",    [cpu.bs('010001'), cpu.bs('01000'), fcc, cpu.bs('0'),
+                     cpu.bs('0'), soff])
 
-mips32op("swc1",    [bs('111001'), base, ft, s16imm_noarg], [ft, base])
+mips32op("swc1",    [cpu.bs('111001'), base, ft, s16imm_noarg], [ft, base])
 
-mips32op("cvt.d",   [bs('010001'), bs_fmt, bs('00000'), fs, fd, bs('100001')], [fd, fs])
-mips32op("cvt.w",   [bs('010001'), bs_fmt, bs('00000'), fs, fd, bs('100100')], [fd, fs])
-mips32op("cvt.s",   [bs('010001'), bs_fmt, bs('00000'), fs, fd, bs('100000')], [fd, fs])
+mips32op("cvt.d",   [cpu.bs('010001'), bs_fmt, cpu.bs('00000'), fs, fd,
+                     cpu.bs('100001')], [fd, fs])
+mips32op("cvt.w",   [cpu.bs('010001'), bs_fmt, cpu.bs('00000'), fs, fd,
+                     cpu.bs('100100')], [fd, fs])
+mips32op("cvt.s",   [cpu.bs('010001'), bs_fmt, cpu.bs('00000'), fs, fd,
+                     cpu.bs('100000')], [fd, fs])
 
-mips32op("ext",     [bs('011111'), rs, rt, esize, epos, bs('000000')], [rt, rs, epos, esize])
-mips32op("ins",     [bs('011111'), rs, rt, eposh, epos, bs('000100')], [rt, rs, epos, eposh])
+mips32op("ext",     [cpu.bs('011111'), rs, rt, esize, epos, cpu.bs('000000')],
+         [rt, rs, epos, esize])
+mips32op("ins",     [cpu.bs('011111'), rs, rt, eposh, epos, cpu.bs('000100')],
+         [rt, rs, epos, eposh])
 
-mips32op("seb",     [bs('011111'), bs('00000'), rt, rd, bs('10000'), bs('100000')], [rd, rt])
-mips32op("seh",     [bs('011111'), bs('00000'), rt, rd, bs('11000'), bs('100000')], [rd, rt])
-mips32op("wsbh",    [bs('011111'), bs('00000'), rt, rd, bs('00010'), bs('100000')], [rd, rt])
+mips32op("seb",     [cpu.bs('011111'), cpu.bs('00000'), rt, rd, cpu.bs('10000'),
+                     cpu.bs('100000')], [rd, rt])
+mips32op("seh",     [cpu.bs('011111'), cpu.bs('00000'), rt, rd, cpu.bs('11000'),
+                     cpu.bs('100000')], [rd, rt])
+mips32op("wsbh",    [cpu.bs('011111'), cpu.bs('00000'), rt, rd, cpu.bs('00010'),
+                     cpu.bs('100000')], [rd, rt])
 
-mips32op("di",      [bs('010000'), bs('01011'), rt, bs('01100'), bs('00000'), bs('0'), bs('00'), bs('000')])
-mips32op("ei",      [bs('010000'), bs('01011'), rt, bs('01100'), bs('00000'), bs('1'), bs('00'), bs('000')])
+mips32op("di",      [cpu.bs('010000'), cpu.bs('01011'), rt, cpu.bs('01100'),
+                     cpu.bs('00000'), cpu.bs('0'), cpu.bs('00'), cpu.bs('000')])
+mips32op("ei",      [cpu.bs('010000'), cpu.bs('01011'), rt, cpu.bs('01100'),
+                     cpu.bs('00000'), cpu.bs('1'), cpu.bs('00'), cpu.bs('000')])
 
 
-mips32op("tlbp",    [bs('010000'), bs('1'), bs('0'*19), bs('001000')])
-mips32op("tlbwi",   [bs('010000'), bs('1'), bs('0'*19), bs('000010')])
+mips32op("tlbp",    [cpu.bs('010000'), cpu.bs('1'), cpu.bs('0'*19),
+                     cpu.bs('001000')])
+mips32op("tlbwi",   [cpu.bs('010000'), cpu.bs('1'), cpu.bs('0'*19),
+                     cpu.bs('000010')])
diff --git a/miasm2/arch/mips32/regs.py b/miasm2/arch/mips32/regs.py
index 64df4b98..7c049cd9 100644
--- a/miasm2/arch/mips32/regs.py
+++ b/miasm2/arch/mips32/regs.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python
 #-*- coding:utf-8 -*-
 
-from miasm2.expression.expression import *
+from miasm2.expression.expression import ExprId
 from miasm2.core.cpu import gen_reg, gen_regs
 
 
@@ -53,9 +53,11 @@ regs_flt_expr, regs_flt_init, fltregs = gen_regs(regs_flt_str, globals(), sz=64)
 regs_fcc_expr, regs_fcc_init, fccregs = gen_regs(regs_fcc_str, globals())
 
 
-all_regs_ids = [PC, PC_FETCH, R_LO, R_HI] + gpregs_expr + regs_flt_expr + regs_fcc_expr
+all_regs_ids = [PC, PC_FETCH, R_LO, R_HI] + gpregs_expr + regs_flt_expr + \
+    regs_fcc_expr
 all_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids])
-all_regs_ids_init = [PC_init, PC_FETCH_init, R_LO_init, R_HI_init] + gpregs_init + regs_flt_init + regs_fcc_init
+all_regs_ids_init = [PC_init, PC_FETCH_init, R_LO_init, R_HI_init] + \
+    gpregs_init + regs_flt_init + regs_fcc_init
 all_regs_ids_no_alias = all_regs_ids[:]
 
 regs_init = {}