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| author | Camille Mougey <commial@gmail.com> | 2015-10-14 17:24:32 +0200 |
|---|---|---|
| committer | Camille Mougey <commial@gmail.com> | 2015-10-14 17:24:32 +0200 |
| commit | e78fbcbb68da29d36066d89743024d51a0240650 (patch) | |
| tree | bf845fe621eb4e7dc7c0f06ceb7852fdc2731a1d | |
| parent | 9acc75956e3f7afc6837fe5da3613a4ddd5565a9 (diff) | |
| parent | bd8099be5a5734446533d1338cb914eb324da5c6 (diff) | |
| download | miasm-e78fbcbb68da29d36066d89743024d51a0240650.tar.gz miasm-e78fbcbb68da29d36066d89743024d51a0240650.zip | |
Merge pull request #227 from serpilliere/fix_aarch64
Fix aarch64
| -rw-r--r-- | miasm2/arch/aarch64/arch.py | 7 | ||||
| -rw-r--r-- | test/arch/aarch64/arch.py | 5 |
2 files changed, 11 insertions, 1 deletions
diff --git a/miasm2/arch/aarch64/arch.py b/miasm2/arch/aarch64/arch.py index 8c439dcc..816d67f4 100644 --- a/miasm2/arch/aarch64/arch.py +++ b/miasm2/arch/aarch64/arch.py @@ -1451,6 +1451,7 @@ rn0 = bs(l=5, cls=(aarch64_gpreg0,), fname="rn") rmz = bs(l=5, cls=(aarch64_gpregz,), fname="rm") rnz = bs(l=5, cls=(aarch64_gpregz,), fname="rn") +rdz = bs(l=5, cls=(aarch64_gpregz,), fname="rd") rn_n1 = bs(l=5, cls=(aarch64_gpreg_n1,), fname="rn") @@ -1602,10 +1603,14 @@ aarch64op("addsub", [sf, bs_adsu_name, modf, bs('01011'), bs('00'), bs('1'), rm_ aarch64op("neg", [sf, bs('1'), modf, bs('01011'), shift, bs('0'), rm_sft, imm6, bs('11111'), rd], [rd, rm_sft], alias=True) -logic_name = {'AND': 0, 'ORR': 1, 'EOR': 2, 'ANDS': 3} +logic_name = {'AND': 0, 'ORR': 1, 'EOR': 2} bs_logic_name = bs_name(l=2, name=logic_name) # logical (imm) aarch64op("logic", [sf, bs_logic_name, bs('100100'), immn, immr, imms, rn0, rd], [rd, rn0, imms]) +# ANDS +aarch64op("ands", [sf, bs('11'), bs('100100'), immn, immr, imms, rn0, rdz], [rdz, rn0, imms]) +aarch64op("tst", [sf, bs('11'), bs('100100'), immn, immr, imms, rn0, bs('11111')], [rn0, imms], alias=True) + # bitfield move p.149 logicbf_name = {'SBFM': 0b00, 'BFM': 0b01, 'UBFM': 0b10} diff --git a/test/arch/aarch64/arch.py b/test/arch/aarch64/arch.py index aa3ab4dd..cca9184a 100644 --- a/test/arch/aarch64/arch.py +++ b/test/arch/aarch64/arch.py @@ -118,6 +118,11 @@ reg_tests_aarch64 = [ "000B1F72"), ("00079A80 ANDS X20, X2, 0xFF", "541C40F2"), + ("XXXXXXXX TST W14, 0x1", + "DF010072"), + ("XXXXXXXX ANDS W12, W13, 0x1", + "AC010072"), + ("0005BD5C AND W0, W0, W24", "0000180A"), |