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| author | William Bruneau <william.bruneau@epfedu.fr> | 2019-02-22 20:13:45 +0100 |
|---|---|---|
| committer | William Bruneau <william.bruneau@epfedu.fr> | 2019-03-28 12:59:12 +0100 |
| commit | f51724fcdb8d3a57f7e3d2b718636e932d36c965 (patch) | |
| tree | 10616270266f63155d94be778faabf744841b1fd | |
| parent | 9a4b9d912de76e9e8dccb20bbae9f8bc352f0de3 (diff) | |
| download | miasm-f51724fcdb8d3a57f7e3d2b718636e932d36c965.tar.gz miasm-f51724fcdb8d3a57f7e3d2b718636e932d36c965.zip | |
Add some x86_cpuid indexes implementations
| -rw-r--r-- | miasm/jitter/op_semantics.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/miasm/jitter/op_semantics.c b/miasm/jitter/op_semantics.c index 79dcdcf4..6725ae64 100644 --- a/miasm/jitter/op_semantics.c +++ b/miasm/jitter/op_semantics.c @@ -380,6 +380,41 @@ unsigned int x86_cpuid(unsigned int a, unsigned int reg_num) return 0x00000000; } } + // Extended Function CPUID Information + else if (a == 0x80000000){ + switch(reg_num){ + case 0: + // Pentium 4 Processor supporting Hyper-Threading + // Technology to Intel Xeon Processor 5100 Series + return 0x80000008; + case 1: + return 0x00000000; + case 2: + return 0x00000000; + case 3: + return 0x00000000; + } + } + else if (a == 0x80000001){ + switch(reg_num){ + case 0: + // Extended Processor Signature and Extended Feature + // Bits + return 0x00000000; + case 1: + return 0x00000000; + case 2: + return (/* LAHF-SAHF */ 1 << 0) + | (/* LZCNT */ 0 << 5) + | (/* PREFETCHW */ 1 << 8); + case 3: + return (/* SYSCALL/SYSRET */ 1 << 11) + | (/* Execute Disable Bit available */ 0 << 20) + | (/* 1-GByte pages available */ 0 << 26) + | (/* RDTSCP and IA32_TSC_AUX available */ 0 << 27) + | (/* Intel ® 64 Architecture available */ 1 << 29); + } + } else{ fprintf(stderr, "WARNING not implemented x86_cpuid index %X!\n", a); exit(EXIT_FAILURE); |