Add preliminary support for PPC MMU registers (#1130)

3 files changed, 75 insertions, 5 deletions

diff --git a/miasm/arch/ppc/regs.py b/miasm/arch/ppc/regs.py
index 97556931..4b710045 100644
--- a/miasm/arch/ppc/regs.py
+++ b/miasm/arch/ppc/regs.py
@@ -46,10 +46,19 @@ superregs_str = (["SPRG%d" % i for i in range(4)] +
 superregs_expr, superregs_init, superregs = gen_regs(superregs_str,
                                                      globals(), 32)
 
+mmuregs_str = (["SR%d" % i for i in range(16)] +
+               ["IBAT%dU" % i for i in range(4)] +
+               ["IBAT%dL" % i for i in range(4)] +
+               ["DBAT%dU" % i for i in range(4)] +
+               ["DBAT%dL" % i for i in range(4)] +
+               ["SDR1"])
+mmuregs_expr, mmuregs_init, mmuregs = gen_regs(mmuregs_str,
+                                               globals(), 32)
+
 regs_flt_expr = []
 
 all_regs_ids = (gpregs_expr + crfbitregs_expr + xerbitregs_expr +
-                xerbcreg_expr + otherregs_expr + superregs_expr +
+                xerbcreg_expr + otherregs_expr + superregs_expr + mmuregs_expr +
                 [ exception_flags, spr_access, reserve, reserve_address ])
 all_regs_ids_byname = dict([(x.name, x) for x in all_regs_ids])
 all_regs_ids_init = [ExprId("%s_init" % x.name, x.size) for x in all_regs_ids]
diff --git a/miasm/arch/ppc/sem.py b/miasm/arch/ppc/sem.py
index 5e8e394c..fd6db8f3 100644
--- a/miasm/arch/ppc/sem.py
+++ b/miasm/arch/ppc/sem.py
@@ -10,9 +10,19 @@ from miasm.jitter.csts import *
 
 spr_dict = {
     8: LR, 9: CTR, 18: DSISR, 19: DAR,
-    22: DEC, 26: SRR0, 27: SRR1,
+    22: DEC, 25: SDR1, 26: SRR0, 27: SRR1,
     272: SPRG0, 273: SPRG0, 274: SPRG1, 275: SPRG2, 276: SPRG3,
-    284: TBL, 285: TBU, 287: PVR, 1023: PIR
+    284: TBL, 285: TBU, 287: PVR,
+    528: IBAT0U, 529: IBAT0L, 530: IBAT1U, 531: IBAT1L, 532: IBAT2U, 533: IBAT2L, 534: IBAT3U, 535: IBAT3L,
+    536: DBAT0U, 537: DBAT0L, 538: DBAT1U, 539: DBAT1L, 540: DBAT2U, 541: DBAT2L, 542: DBAT3U, 543: DBAT3L,
+    1023: PIR
+}
+
+sr_dict = {
+    0: SR0, 1: SR1, 2: SR2, 3: SR3,
+    4: SR4, 5: SR5, 6: SR6, 7: SR7,
+    8: SR8, 9: SR9, 10: SR10, 11: SR11,
+    12: SR12, 13: SR13, 14: SR14, 15: SR15
 }
 
 crf_dict = dict((ExprId("CR%d" % i, 4),
@@ -23,6 +33,7 @@ crf_dict = dict((ExprId("CR%d" % i, 4),
 ctx = {
     'crf_dict': crf_dict,
     'spr_dict': spr_dict,
+    'sr_dict': sr_dict,
     'expr': expr,
 }
 
@@ -384,6 +395,22 @@ def mn_mtspr(ir, instr, arg1, arg2):
                                     SPR_ACCESS_IS_WRITE), 32)),
                  ExprAssign(exception_flags, ExprInt(EXCEPT_SPR_ACCESS, 32)) ], []
 
+def mn_mtsr(ir, instr, sr, rs):
+    srid = sr.arg.arg
+    return [ ExprAssign(sr_dict[srid], rs) ], []
+
+# TODO
+#def mn_mtsrin(ir, instr, rs, rb):
+#    return [ ExprAssign(sr_dict[rb[0:3]], rs) ], []
+
+def mn_mfsr(ir, instr, rd, sr):
+    srid = sr.arg.arg
+    return [ ExprAssign(rd, sr_dict[srid]) ], []
+
+# TODO
+#def mn_mfsrin(ir, instr, rd, rb):
+#    return [ ExprAssign(rd, sr_dict[rb[0:3]]) ], []
+
 def mn_do_mul(ir, instr, rd, ra, arg2):
     variant = instr.name[3:]
     if variant[-1] == '.':
@@ -809,13 +836,13 @@ sem_dir = {
     'MFCR': mn_do_mfcr,
     'MFMSR': mn_mfmsr,
     'MFSPR': mn_mfspr,
-    'MFSR': mn_do_nop_warn,
+    'MFSR': mn_mfsr,
     'MFSRIN': mn_do_nop_warn,
     'MFTB': mn_mfmsr,
     'MTCRF': mn_mtcrf,
     'MTMSR': mn_mtmsr,
     'MTSPR': mn_mtspr,
-    'MTSR': mn_do_nop_warn,
+    'MTSR': mn_mtsr,
     'MTSRIN': mn_do_nop_warn,
     'NAND': mn_do_nand,
     'NAND.': mn_do_nand,
diff --git a/miasm/jitter/arch/JitCore_ppc32_regs.h b/miasm/jitter/arch/JitCore_ppc32_regs.h
index d15b5e51..a16d1e95 100644
--- a/miasm/jitter/arch/JitCore_ppc32_regs.h
+++ b/miasm/jitter/arch/JitCore_ppc32_regs.h
@@ -87,3 +87,37 @@ JITCORE_PPC_REG_EXPAND(PVR, 32)
 JITCORE_PPC_REG_EXPAND(DEC, 32)
 JITCORE_PPC_REG_EXPAND(TBL, 32)
 JITCORE_PPC_REG_EXPAND(TBU, 32)
+
+JITCORE_PPC_REG_EXPAND(SR0, 32)
+JITCORE_PPC_REG_EXPAND(SR1, 32)
+JITCORE_PPC_REG_EXPAND(SR2, 32)
+JITCORE_PPC_REG_EXPAND(SR3, 32)
+JITCORE_PPC_REG_EXPAND(SR4, 32)
+JITCORE_PPC_REG_EXPAND(SR5, 32)
+JITCORE_PPC_REG_EXPAND(SR6, 32)
+JITCORE_PPC_REG_EXPAND(SR7, 32)
+JITCORE_PPC_REG_EXPAND(SR8, 32)
+JITCORE_PPC_REG_EXPAND(SR9, 32)
+JITCORE_PPC_REG_EXPAND(SR10, 32)
+JITCORE_PPC_REG_EXPAND(SR11, 32)
+JITCORE_PPC_REG_EXPAND(SR12, 32)
+JITCORE_PPC_REG_EXPAND(SR13, 32)
+JITCORE_PPC_REG_EXPAND(SR14, 32)
+JITCORE_PPC_REG_EXPAND(SR15, 32)
+JITCORE_PPC_REG_EXPAND(IBAT0U, 32)
+JITCORE_PPC_REG_EXPAND(IBAT0L, 32)
+JITCORE_PPC_REG_EXPAND(IBAT1U, 32)
+JITCORE_PPC_REG_EXPAND(IBAT1L, 32)
+JITCORE_PPC_REG_EXPAND(IBAT2U, 32)
+JITCORE_PPC_REG_EXPAND(IBAT2L, 32)
+JITCORE_PPC_REG_EXPAND(IBAT3U, 32)
+JITCORE_PPC_REG_EXPAND(IBAT3L, 32)
+JITCORE_PPC_REG_EXPAND(DBAT0U, 32)
+JITCORE_PPC_REG_EXPAND(DBAT0L, 32)
+JITCORE_PPC_REG_EXPAND(DBAT1U, 32)
+JITCORE_PPC_REG_EXPAND(DBAT1L, 32)
+JITCORE_PPC_REG_EXPAND(DBAT2U, 32)
+JITCORE_PPC_REG_EXPAND(DBAT2L, 32)
+JITCORE_PPC_REG_EXPAND(DBAT3U, 32)
+JITCORE_PPC_REG_EXPAND(DBAT3L, 32)
+JITCORE_PPC_REG_EXPAND(SDR1, 32)