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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-03-11 18:46:19 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-04-18 09:54:48 +0200 |
| commit | 94acdee558688cabd85fc7f4beb216e73ecabfbd (patch) | |
| tree | 3638c8321eea40e4d0c4c1edbc1412fd1ca4cac5 | |
| parent | b5b8c0626e12f779404606362151c3e373aaa673 (diff) | |
| download | miasm-94acdee558688cabd85fc7f4beb216e73ecabfbd.tar.gz miasm-94acdee558688cabd85fc7f4beb216e73ecabfbd.zip | |
Fix armt ir
| -rw-r--r-- | miasm2/arch/arm/ira.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py index bfa9bad2..cfcb294c 100644 --- a/miasm2/arch/arm/ira.py +++ b/miasm2/arch/arm/ira.py @@ -47,11 +47,11 @@ class ir_a_armb(ir_a_armb_base, ir_a_arml): class ir_a_armtl(ir_armtl, ir_a_arml): - def __init__(self, symbol_pool): + def __init__(self, symbol_pool=None): ir_armtl.__init__(self, symbol_pool) self.ret_reg = self.arch.regs.R0 class ir_a_armtb(ir_a_armtl, ir_armtb, ir_a_armb): - def __init__(self, symbol_pool): + def __init__(self, symbol_pool=None): ir_armtb.__init__(self, symbol_pool) self.ret_reg = self.arch.regs.R0 |