Merge pull request #675 from serpilliere/fix_aarch64_shift

Fix aarch64 shift

4 files changed, 31 insertions, 9 deletions

diff --git a/miasm2/arch/aarch64/regs.py b/miasm2/arch/aarch64/regs.py
index 4589c17a..f2655ea7 100644
--- a/miasm2/arch/aarch64/regs.py
+++ b/miasm2/arch/aarch64/regs.py
@@ -4,6 +4,7 @@ from miasm2.expression.expression import *
 from miasm2.core.cpu import gen_reg, gen_regs
 
 exception_flags = ExprId('exception_flags', 32)
+interrupt_num = ExprId('interrupt_num', 32)
 
 
 gpregs32_str = ["W%d" % i for i in xrange(0x1f)] + ["WSP"]
@@ -86,7 +87,7 @@ all_regs_ids = [
     X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16,
     X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, LR, SP,
 
-    exception_flags,
+    exception_flags, interrupt_num,
     PC,
     WZR,
     zf, nf, of, cf,
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py
index a575c819..697fa981 100644
--- a/miasm2/arch/aarch64/sem.py
+++ b/miasm2/arch/aarch64/sem.py
@@ -3,7 +3,7 @@ from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock
 from miasm2.arch.aarch64.arch import mn_aarch64, conds_expr, replace_regs
 from miasm2.arch.aarch64.regs import *
 from miasm2.core.sembuilder import SemBuilder
-from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO
+from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO, EXCEPT_INT_XX
 
 
 # CPSR: N Z C V
@@ -126,11 +126,14 @@ def extend_arg(dst, arg):
     op, (reg, shift) = arg.op, arg.args
     if op == 'SXTW':
         base = reg.signExtend(dst.size)
-    else:
+        op = "<<"
+    elif op in ['<<', '>>', '<<a', 'a>>', '<<<', '>>>']:
         base = reg.zeroExtend(dst.size)
+    else:
+        raise NotImplementedError('Unknown shifter operator')
 
-    out = base << (shift.zeroExtend(dst.size)
-                   & m2_expr.ExprInt(dst.size - 1, dst.size))
+    out = ExprOp(op, base, (shift.zeroExtend(dst.size)
+                            & m2_expr.ExprInt(dst.size - 1, dst.size)))
     return out
 
 
@@ -145,7 +148,9 @@ ctx = {"PC": PC,
        "extend_arg": extend_arg,
        "m2_expr":m2_expr,
        "exception_flags": exception_flags,
+       "interrupt_num": interrupt_num,
        "EXCEPT_DIV_BY_ZERO": EXCEPT_DIV_BY_ZERO,
+       "EXCEPT_INT_XX": EXCEPT_INT_XX,
        }
 
 sbuild = SemBuilder(ctx)
@@ -196,7 +201,7 @@ def orn(arg1, arg2, arg3):
 @sbuild.parse
 def bic(arg1, arg2, arg3):
     arg1 = arg2 & (~extend_arg(arg2, arg3))
-    
+
 
 def bics(ir, instr, arg1, arg2, arg3):
     e = []
@@ -717,6 +722,12 @@ def extr(arg1, arg2, arg3, arg4):
     compose = m2_expr.ExprCompose(arg2, arg3)
     arg1 = compose[int(arg4.arg):int(arg4)+arg1.size]
 
+
+@sbuild.parse
+def svc(arg1):
+    exception_flags = m2_expr.ExprInt(EXCEPT_INT_XX, exception_flags.size)
+    interrupt_num = m2_expr.ExprInt(int(arg1), interrupt_num.size)
+
 mnemo_func = sbuild.functions
 mnemo_func.update({
     'and': and_l,
@@ -743,9 +754,9 @@ mnemo_func.update({
     'b.le': b_le,
     'b.ls': b_ls,
     'b.lt': b_lt,
-    
+
     'bics': bics,
-    
+
     'ret': ret,
     'stp': stp,
     'ldp': ldp,
@@ -814,7 +825,6 @@ class ir_aarch64l(IntermediateRepresentation):
         instr_ir, extra_ir = get_mnemo_expr(self, instr, *args)
         self.mod_pc(instr, instr_ir, extra_ir)
         instr_ir, extra_ir = self.del_dst_zr(instr, instr_ir, extra_ir)
-
         return instr_ir, extra_ir
 
     def expr_fix_regs_for_mode(self, e):
diff --git a/miasm2/jitter/arch/JitCore_aarch64.c b/miasm2/jitter/arch/JitCore_aarch64.c
index 03113d30..e10d847e 100644
--- a/miasm2/jitter/arch/JitCore_aarch64.c
+++ b/miasm2/jitter/arch/JitCore_aarch64.c
@@ -50,6 +50,10 @@ reg_dict gpreg_dict[] = {
 	{.name = "nf", .offset = offsetof(vm_cpu_t, nf)},
 	{.name = "of", .offset = offsetof(vm_cpu_t, of)},
 	{.name = "cf", .offset = offsetof(vm_cpu_t, cf)},
+
+	{.name = "exception_flags", .offset = offsetof(vm_cpu_t, exception_flags)},
+	{.name = "interrupt_num", .offset = offsetof(vm_cpu_t, interrupt_num)},
+
 };
 
 /************************** JitCpu object **************************/
@@ -375,6 +379,9 @@ getset_reg_u32(of);
 getset_reg_u32(cf);
 
 
+getset_reg_u32(exception_flags);
+getset_reg_u32(interrupt_num);
+
 
 PyObject* get_gpreg_offset_all(void)
 {
@@ -485,6 +492,9 @@ static PyGetSetDef JitCpu_getseters[] = {
     {"of", (getter)JitCpu_get_of, (setter)JitCpu_set_of, "of", NULL},
     {"cf", (getter)JitCpu_get_cf, (setter)JitCpu_set_cf, "cf", NULL},
 
+    {"exception_flags", (getter)JitCpu_get_exception_flags, (setter)JitCpu_set_exception_flags, "exception_flags", NULL},
+    {"interrupt_num", (getter)JitCpu_get_interrupt_num, (setter)JitCpu_set_interrupt_num, "interrupt_num", NULL},
+
     {NULL}  /* Sentinel */
 };
 
diff --git a/miasm2/jitter/arch/JitCore_aarch64.h b/miasm2/jitter/arch/JitCore_aarch64.h
index 4635b395..c7fc3cea 100644
--- a/miasm2/jitter/arch/JitCore_aarch64.h
+++ b/miasm2/jitter/arch/JitCore_aarch64.h
@@ -1,6 +1,7 @@
 
 typedef struct {
 	uint32_t exception_flags;
+	uint32_t interrupt_num;
 
 	/* gpregs */