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| author | Camille Mougey <commial@gmail.com> | 2017-04-27 07:53:45 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-04-27 07:53:45 +0200 |
| commit | ca1482ebc82e768f6113eac90cfe56e82a720cd7 (patch) | |
| tree | 0f33cad14ba2dd46c967f9f37b226aab2d348b45 | |
| parent | 968e8fff0b9caef2441d005787897d44efaf860a (diff) | |
| parent | 87091c19c513022f05a44cb0601572155f6a74e1 (diff) | |
| download | miasm-ca1482ebc82e768f6113eac90cfe56e82a720cd7.tar.gz miasm-ca1482ebc82e768f6113eac90cfe56e82a720cd7.zip | |
Merge pull request #538 from serpilliere/fix_cpu_reg_int
Jitter: Error on reg set not int
| -rw-r--r-- | miasm2/jitter/JitCore.h | 13 | ||||
| -rw-r--r-- | miasm2/jitter/arch/JitCore_x86.c | 4 |
2 files changed, 9 insertions, 8 deletions
diff --git a/miasm2/jitter/JitCore.h b/miasm2/jitter/JitCore.h index 24feb9c0..f599d6ea 100644 --- a/miasm2/jitter/JitCore.h +++ b/miasm2/jitter/JitCore.h @@ -17,7 +17,7 @@ } \ -#define PyGetInt_ret0(item, value) \ +#define PyGetInt_retneg(item, value) \ if (PyInt_Check(item)){ \ value = (uint64_t)PyInt_AsLong(item); \ } \ @@ -25,7 +25,8 @@ value = (uint64_t)PyLong_AsUnsignedLongLong(item); \ } \ else{ \ - printf("error\n"); return 0; \ + PyErr_SetString(PyExc_TypeError, "Arg must be int"); \ + return -1; \ } \ @@ -38,7 +39,7 @@ static int JitCpu_set_ ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint64_t val; \ - PyGetInt_ret0(value, val); \ + PyGetInt_retneg(value, val); \ ((vm_cpu_t*)(self->cpu))-> regname = val; \ return 0; \ } @@ -51,7 +52,7 @@ static int JitCpu_set_ ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint32_t val; \ - PyGetInt_ret0(value, val); \ + PyGetInt_retneg(value, val); \ ((vm_cpu_t*)(self->cpu))-> regname = val; \ return 0; \ } @@ -65,8 +66,8 @@ static int JitCpu_set_ ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint16_t val; \ - PyGetInt_ret0(value, val); \ - ((vm_cpu_t*)(self->cpu))-> regname = val; \ + PyGetInt_retneg(value, val); \ + ((vm_cpu_t*)(self->cpu))-> regname = val; \ return 0; \ } diff --git a/miasm2/jitter/arch/JitCore_x86.c b/miasm2/jitter/arch/JitCore_x86.c index 95cb18bd..3198eff3 100644 --- a/miasm2/jitter/arch/JitCore_x86.c +++ b/miasm2/jitter/arch/JitCore_x86.c @@ -428,7 +428,7 @@ JitCpu_init(JitCpu *self, PyObject *args, PyObject *kwds) static int JitCpu_set_E ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint64_t val; \ - PyGetInt_ret0(value, val); \ + PyGetInt_retneg(value, val); \ val &= 0xFFFFFFFF; \ val |= ((vm_cpu_t*)(self->cpu))->R ##regname & 0xFFFFFFFF00000000ULL; \ ((vm_cpu_t*)(self->cpu))->R ## regname = val; \ @@ -445,7 +445,7 @@ JitCpu_init(JitCpu *self, PyObject *args, PyObject *kwds) static int JitCpu_set_ ## regname (JitCpu *self, PyObject *value, void *closure) \ { \ uint64_t val; \ - PyGetInt_ret0(value, val); \ + PyGetInt_retneg(value, val); \ val &= 0xFFFF; \ val |= ((vm_cpu_t*)(self->cpu))->R ##regname & 0xFFFFFFFFFFFF0000ULL; \ ((vm_cpu_t*)(self->cpu))->R ## regname = val; \ |