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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2019-03-18 09:06:32 +0100 |
|---|---|---|
| committer | serpilliere <serpilliere@droids-corp.org> | 2020-02-14 16:41:23 +0100 |
| commit | 215c5ebfe9d0beed56f9391cb517ccbb7fa4f4f8 (patch) | |
| tree | 37fef0c8bf6d0daed22ad73bcf1dfa4295280ab5 /example/disasm/full.py | |
| parent | fc6bb3ce49ea44012a762b207a39301825e9648a (diff) | |
| download | miasm-215c5ebfe9d0beed56f9391cb517ccbb7fa4f4f8.tar.gz miasm-215c5ebfe9d0beed56f9391cb517ccbb7fa4f4f8.zip | |
Analysis: dead simp to class
Diffstat (limited to 'example/disasm/full.py')
| -rw-r--r-- | example/disasm/full.py | 37 |
1 files changed, 2 insertions, 35 deletions
diff --git a/example/disasm/full.py b/example/disasm/full.py index a28d548e..d4fae867 100644 --- a/example/disasm/full.py +++ b/example/disasm/full.py @@ -9,7 +9,7 @@ from miasm.analysis.binary import Container from miasm.core.asmblock import log_asmblock, AsmCFG from miasm.core.interval import interval from miasm.analysis.machine import Machine -from miasm.analysis.data_flow import dead_simp, \ +from miasm.analysis.data_flow import \ DiGraphDefUse, ReachingDefinitions, \ replace_stack_vars, load_from_int, del_unused_edges from miasm.expression.simplifications import expr_simp @@ -213,7 +213,6 @@ if args.propagexpr: class IRADelModCallStack(ira): - def call_effects(self, addr, instr): assignblks, extra = super(IRADelModCallStack, self).call_effects(addr, instr) if not args.calldontmodstack: @@ -283,34 +282,6 @@ if args.gen_ir: if args.propagexpr: - class IRAOutRegs(ira): - def get_out_regs(self, block): - regs_todo = super(self.__class__, self).get_out_regs(block) - out = {} - for assignblk in block: - for dst in assignblk: - reg = self.ssa_var.get(dst, None) - if reg is None: - continue - if reg in regs_todo: - out[reg] = dst - return set(viewvalues(out)) - - # Add dummy dependency to uncover out regs assignment - for loc in ircfg_a.leaves(): - irblock = ircfg_a.blocks.get(loc) - if irblock is None: - continue - regs = {} - for reg in ir_arch_a.get_out_regs(irblock): - regs[reg] = reg - assignblks = list(irblock) - new_assiblk = AssignBlock(regs, assignblks[-1].instr) - assignblks.append(new_assiblk) - new_irblock = IRBlock(irblock.loc_key, assignblks) - ircfg_a.blocks[loc] = new_irblock - - def is_addr_ro_variable(bs, addr, size): """ @@ -327,9 +298,6 @@ if args.propagexpr: return False return True - ir_arch_a = IRAOutRegs(mdis.loc_db) - - class CustomIRCFGSimplifierSSA(IRCFGSimplifierSSA): def do_simplify(self, ssa, head): modified = super(CustomIRCFGSimplifierSSA, self).do_simplify(ssa, head) @@ -345,14 +313,13 @@ if args.propagexpr: replace_stack_vars(self.ir_arch, ircfg) ircfg_simplifier = IRCFGSimplifierCommon(self.ir_arch) + ircfg_simplifier.deadremoval.add_expr_to_original_expr(ssa.ssa_variable_to_expr) ircfg_simplifier.simplify(ircfg, head) return ircfg - head = list(entry_points)[0] - ir_arch_a = IRAOutRegs(mdis.loc_db) simplifier = CustomIRCFGSimplifierSSA(ir_arch_a) ircfg = simplifier.simplify(ircfg_a, head) open('final.dot', 'w').write(ircfg.dot()) |