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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-08-14 21:20:16 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-08-14 21:20:16 +0200 |
| commit | c8d20b8f1a58e01b9b43eff4b29866c8b388e3b8 (patch) | |
| tree | e08cd9dbd13f822313fa5123dc9cb63e73abd40d /example/ida | |
| parent | 745f3e995995968d36b762c7159cacef1243e4c6 (diff) | |
| download | miasm-c8d20b8f1a58e01b9b43eff4b29866c8b388e3b8.tar.gz miasm-c8d20b8f1a58e01b9b43eff4b29866c8b388e3b8.zip | |
Example/ctype: fix propagation on mem write
Display the destination type if it's a memory variable, and we know its type (we consider source and destination have the same type).
Diffstat (limited to 'example/ida')
| -rw-r--r-- | example/ida/ctype_propagation.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/example/ida/ctype_propagation.py b/example/ida/ctype_propagation.py index 7eb209cd..c18abbfd 100644 --- a/example/ida/ctype_propagation.py +++ b/example/ida/ctype_propagation.py @@ -123,7 +123,9 @@ class SymbExecCTypeFix(SymbExecCType): # Replace PC with value to match IR args pc_fixed = {self.ir_arch.pc: m2_expr.ExprInt(instr.offset + instr.l, self.ir_arch.pc.size)} - for arg in tmp_r: + inputs = tmp_r + inputs.update(arg for arg in tmp_w if arg.is_mem()) + for arg in inputs: arg = expr_simp(arg.replace_expr(pc_fixed)) if arg in tmp_w and not arg.is_mem(): continue |