Modify irbloc destination mecanism. Rework API in consequence.

Fat patch here: some API have changed.

Each irbloc now affects a special "IRDst" register which is used to
describe the destination irbloc. It allows simple description of
architectures using delay slots. Architectures semantic and tcc/python
jitter are modified in consequence. LLVM jitter is disabled for now,
but should be patch soon.

1 files changed, 6 insertions, 6 deletions

diff --git a/example/test_dis.py b/example/test_dis.py
index ef314893..dc3f7274 100644
--- a/example/test_dis.py
+++ b/example/test_dis.py
@@ -223,19 +223,19 @@ log.info('total lines %s' % total_l)
 if options.gen_ir:
     log.info("generating IR")
 
-    my_ir = ira(mdis.symbol_pool)
-    my_ir.blocs = {}
+    ir_arch = ira(mdis.symbol_pool)
+    ir_arch.blocs = {}
     for ad, all_bloc in all_funcs_blocs.items():
         log.info("generating IR... %x" % ad)
         for b in all_bloc:
-            my_ir.add_bloc(b)
+            ir_arch.add_bloc(b)
 
     log.info("Gen Graph... %x" % ad)
 
-    my_ir.gen_graph()
+    ir_arch.gen_graph()
 
     if options.simplify:
-        my_ir.dead_simp()
+        ir_arch.dead_simp()
 
-    out = my_ir.graph()
+    out = ir_arch.graph()
     open('graph_irflow.txt', 'w').write(out)