about summary refs log tree commit diff stats
path: root/miasm2/analysis/dse.py
diff options
context:
space:
mode:
authorAjax <commial@gmail.com>2018-06-11 10:50:00 +0200
committerAjax <commial@gmail.com>2018-06-11 10:50:00 +0200
commitacc6587c46e26810bc4c84cf71b19d95bcc69b23 (patch)
tree28e831895dc0fe5fc480f32a80b63ed570e459c8 /miasm2/analysis/dse.py
parent0fa0cadf55948d6ff8f53eb3bb81ead4ef267b86 (diff)
downloadmiasm-acc6587c46e26810bc4c84cf71b19d95bcc69b23.tar.gz
miasm-acc6587c46e26810bc4c84cf71b19d95bcc69b23.zip
DSE: remove useless changes introduced by 61551fa7
Diffstat (limited to 'miasm2/analysis/dse.py')
-rw-r--r--miasm2/analysis/dse.py9
1 files changed, 2 insertions, 7 deletions
diff --git a/miasm2/analysis/dse.py b/miasm2/analysis/dse.py
index 0502ea42..6eaf1e91 100644
--- a/miasm2/analysis/dse.py
+++ b/miasm2/analysis/dse.py
@@ -63,7 +63,6 @@ from miasm2.expression.expression_helper import possible_values
 from miasm2.ir.translators import Translator
 from miasm2.analysis.expression_range import expr_range
 from miasm2.analysis.modularintervals import ModularIntervals
-from miasm2.core.asmblock import AsmBlockBad
 
 DriftInfo = namedtuple("DriftInfo", ["symbol", "computed", "expected"])
 
@@ -326,8 +325,7 @@ class DSEEngine(object):
 
             ## Update current state
             asm_block = self.mdis.dis_block(cur_addr)
-            if not isinstance(asm_block, AsmBlockBad):
-                self.ir_arch.add_block(asm_block)
+            self.ir_arch.add_block(asm_block)
             self.addr_to_cacheblocks[cur_addr] = dict(self.ir_arch.blocks)
 
         # Emulate the current instruction
@@ -351,14 +349,11 @@ class DSEEngine(object):
 
                 if not (isinstance(next_addr_concrete, ExprLoc) and
                         self.ir_arch.symbol_pool.loc_key_to_offset(
-                            next_addr_concrete
+                            next_addr_concrete.loc_key
                         ) is None):
                     # Not a lbl_gen, exit
                     break
 
-                if self.symb.ir_arch.get_block(cur_addr) is None:
-                    break
-
                 # Call handle with lbl_gen state
                 self.handle(next_addr_concrete)
                 cur_addr = next_addr_concrete