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authorFabrice Desclaux <fabrice.desclaux@cea.fr>2015-08-03 12:38:39 +0200
committerFabrice Desclaux <fabrice.desclaux@cea.fr>2015-08-08 23:45:57 +0200
commitfce9df699d49c5b0907e37d7da7eb30e623805b7 (patch)
tree10b6bde5230da3ccba3a8f186d738b96ee3098e6 /miasm2/analysis/machine.py
parent6278a910630e603a97b7e6d3d34a9780d86719cc (diff)
downloadmiasm-fce9df699d49c5b0907e37d7da7eb30e623805b7.tar.gz
miasm-fce9df699d49c5b0907e37d7da7eb30e623805b7.zip
Add arch aarch64
Diffstat (limited to 'miasm2/analysis/machine.py')
-rw-r--r--miasm2/analysis/machine.py17
1 files changed, 16 insertions, 1 deletions
diff --git a/miasm2/analysis/machine.py b/miasm2/analysis/machine.py
index 778c5def..f963628c 100644
--- a/miasm2/analysis/machine.py
+++ b/miasm2/analysis/machine.py
@@ -12,7 +12,8 @@ class Machine(object):
     __gdbserver = None    # GdbServer handler
 
     __available = ["arml", "armb", "armtl", "armtb", "sh4", "x86_16", "x86_32",
-                   "x86_64", "msp430", "mips32b", "mips32l"]
+                   "x86_64", "msp430", "mips32b", "mips32l",
+                   "aarch64l", "aarch64b"]
 
 
     def __init__(self, machine_name):
@@ -43,6 +44,20 @@ class Machine(object):
             jitter = jit.jitter_armb
             from miasm2.arch.arm.ira import ir_a_armb as ira
             from miasm2.arch.arm.sem import ir_armb as ir
+        elif machine_name == "aarch64l":
+            from miasm2.arch.aarch64.disasm import dis_aarch64l as dis_engine
+            from miasm2.arch.aarch64 import arch, jit
+            mn = arch.mn_aarch64
+            jitter = jit.jitter_aarch64l
+            from miasm2.arch.aarch64.ira import ir_a_aarch64l as ira
+            from miasm2.arch.aarch64.sem import ir_aarch64l as ir
+        elif machine_name == "aarch64b":
+            from miasm2.arch.aarch64.disasm import dis_aarch64b as dis_engine
+            from miasm2.arch.aarch64 import arch, jit
+            mn = arch.mn_aarch64
+            jitter = jit.jitter_aarch64b
+            from miasm2.arch.aarch64.ira import ir_a_aarch64b as ira
+            from miasm2.arch.aarch64.sem import ir_aarch64b as ir
         elif machine_name == "armtl":
             from miasm2.arch.arm.disasm import dis_armtl as dis_engine
             from miasm2.arch.arm import arch