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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-09 15:45:42 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-09 15:59:17 +0100 |
| commit | c77ba7b54724e8fd0c8397f1487e7014bcc56585 (patch) | |
| tree | 8e5a08ab067961e1fb05f53e9b4baacbbdcc5183 /miasm2/arch/aarch64/sem.py | |
| parent | c2e52be18ddd2eeb86b413e851a3ade0ceeca1dc (diff) | |
| download | miasm-c77ba7b54724e8fd0c8397f1487e7014bcc56585.tar.gz miasm-c77ba7b54724e8fd0c8397f1487e7014bcc56585.zip | |
Aarch64/sem: fix extend_op
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/aarch64/sem.py | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index a575c819..4f0b5241 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -126,11 +126,14 @@ def extend_arg(dst, arg): op, (reg, shift) = arg.op, arg.args if op == 'SXTW': base = reg.signExtend(dst.size) - else: + op = "<<" + elif op in ['<<', '>>', '<<a', 'a>>', '<<<', '>>>']: base = reg.zeroExtend(dst.size) + else: + raise NotImplementedError('Unknown shifter operator') - out = base << (shift.zeroExtend(dst.size) - & m2_expr.ExprInt(dst.size - 1, dst.size)) + out = ExprOp(op, base, (shift.zeroExtend(dst.size) + & m2_expr.ExprInt(dst.size - 1, dst.size))) return out |