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| author | Camille Mougey <commial@gmail.com> | 2018-06-22 10:28:38 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-06-22 10:28:38 +0200 |
| commit | 9f040a7013f471ecb96c5f64e5ab3f139d1a09c7 (patch) | |
| tree | f4f21334788d6c153ce08cead01e614349cdf700 /miasm2/arch/arm/arch.py | |
| parent | 1c64ca68ff3ad2985d2c89b4b8a8e13ec282c0e1 (diff) | |
| parent | 189d72985236b0b35586669e7d9309951ffdccb6 (diff) | |
| download | miasm-9f040a7013f471ecb96c5f64e5ab3f139d1a09c7.tar.gz miasm-9f040a7013f471ecb96c5f64e5ab3f139d1a09c7.zip | |
Merge branch 'master' into patch-2
Diffstat (limited to 'miasm2/arch/arm/arch.py')
| -rw-r--r-- | miasm2/arch/arm/arch.py | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py index 17b57ba4..624642cf 100644 --- a/miasm2/arch/arm/arch.py +++ b/miasm2/arch/arm/arch.py @@ -1038,16 +1038,12 @@ class arm_op2(arm_arg): shift_kind = shift & 1 shift_type = (shift >> 1) & 3 shift >>= 3 - # print self.parent.immop.value, hex(shift), hex(shift_kind), - # hex(shift_type) if shift_kind: # shift kind is reg if shift & 1: - # log.debug('error in shift1') return False rs = shift >> 1 if rs == 0xf: - # log.debug('error in shift2') return False shift_op = regs_expr[rs] else: @@ -2155,12 +2151,10 @@ class armt_rlist_pclr(armt_rlist): reg_l = list(e.args) self.parent.pclr.value = 0 if self.parent.pp.value == 0: - # print 'push' if regs_expr[14] in reg_l: reg_l.remove(regs_expr[14]) self.parent.pclr.value = 1 else: - # print 'pop', if regs_expr[15] in reg_l: reg_l.remove(regs_expr[15]) self.parent.pclr.value = 1 |