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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-02-14 19:58:57 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-03-13 14:10:35 +0100 |
| commit | e94fb099ce7cf80f57d21306de4c2b59ce7b3006 (patch) | |
| tree | 5c3f23edb7451622c21b5bce32b18bc87b2e10df /miasm2/arch/arm/ira.py | |
| parent | 73828c4be50c21eae080d0e2150093a8641baab0 (diff) | |
| download | miasm-e94fb099ce7cf80f57d21306de4c2b59ce7b3006.tar.gz miasm-e94fb099ce7cf80f57d21306de4c2b59ce7b3006.zip | |
Arch: clean ira/jit
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/arm/ira.py | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py index 7f5e8f1b..760e6d90 100644 --- a/miasm2/arch/arm/ira.py +++ b/miasm2/arch/arm/ira.py @@ -1,11 +1,7 @@ #-*- coding:utf-8 -*- -from miasm2.expression.expression import * -from miasm2.ir.ir import IRBlock, AssignBlock from miasm2.ir.analysis import ira from miasm2.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb -from miasm2.arch.arm.regs import * -# from miasm2.core.graph import DiGraph class ir_a_arml_base(ir_arml, ira): @@ -26,13 +22,13 @@ class ir_a_arml(ir_a_arml_base): self.ret_reg = self.arch.regs.R0 # for test XXX TODO - def set_dead_regs(self, b): - b.rw[-1][1].add(self.arch.regs.zf) - b.rw[-1][1].add(self.arch.regs.nf) - b.rw[-1][1].add(self.arch.regs.of) - b.rw[-1][1].add(self.arch.regs.cf) + def set_dead_regs(self, irblock): + irblock.rw[-1][1].add(self.arch.regs.zf) + irblock.rw[-1][1].add(self.arch.regs.nf) + irblock.rw[-1][1].add(self.arch.regs.of) + irblock.rw[-1][1].add(self.arch.regs.cf) - def get_out_regs(self, b): + def get_out_regs(self, _): return set([self.ret_reg, self.sp]) def sizeof_char(self): |