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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-10-09 17:04:36 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-10-09 17:04:36 +0200 |
| commit | 7101a6d9d5998102d0dc6a86ac01ba332fed3506 (patch) | |
| tree | 2981aa9d677f614f0ded8476f6e86c20e6c28107 /miasm2/arch/arm/ira.py | |
| parent | 59ef1b1d854cac3e94cd4565a0ac750de9a4c92d (diff) | |
| download | miasm-7101a6d9d5998102d0dc6a86ac01ba332fed3506.tar.gz miasm-7101a6d9d5998102d0dc6a86ac01ba332fed3506.zip | |
Arch/jit: add endianess support jitters
Diffstat (limited to 'miasm2/arch/arm/ira.py')
| -rw-r--r-- | miasm2/arch/arm/ira.py | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py index b92800e7..8cfe2da0 100644 --- a/miasm2/arch/arm/ira.py +++ b/miasm2/arch/arm/ira.py @@ -4,22 +4,26 @@ from miasm2.expression.expression import * from miasm2.ir.ir import ir, irbloc from miasm2.ir.analysis import ira -from miasm2.arch.arm.sem import ir_arm, ir_armt +from miasm2.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb from miasm2.arch.arm.regs import * # from miasm2.core.graph import DiGraph -class ir_a_arm_base(ir_arm, ira): +class ir_a_arml_base(ir_arml, ira): + def __init__(self, symbol_pool=None): + ir_arml.__init__(self, symbol_pool) + self.ret_reg = self.arch.regs.R0 +class ir_a_armb_base(ir_armb, ira): def __init__(self, symbol_pool=None): - ir_arm.__init__(self, symbol_pool) + ir_armb.__init__(self, symbol_pool) self.ret_reg = self.arch.regs.R0 -class ir_a_arm(ir_a_arm_base): +class ir_a_arml(ir_a_arml_base): def __init__(self, symbol_pool=None): - ir_a_arm_base.__init__(self, symbol_pool) + ir_a_arml_base.__init__(self, symbol_pool) self.ret_reg = self.arch.regs.R0 # for test XXX TODO @@ -120,9 +124,19 @@ class ir_a_arm(ir_a_arm_base): def sizeof_pointer(self): return 32 +class ir_a_armb(ir_a_armb_base, ir_a_arml): + + def __init__(self, symbol_pool=None): + ir_a_armb_base.__init__(self, symbol_pool) + self.ret_reg = self.arch.regs.R0 + -class ir_a_armt(ir_armt, ir_a_arm): +class ir_a_armtl(ir_armtl, ir_a_arml): + def __init__(self, symbol_pool): + ir_armtl.__init__(self, symbol_pool) + self.ret_reg = self.arch.regs.R0 +class ir_a_armtb(ir_a_armtl, ir_armtb, ir_a_armb): def __init__(self, symbol_pool): - ir_armt.__init__(self, symbol_pool) + ir_armtb.__init__(self, symbol_pool) self.ret_reg = self.arch.regs.R0 |