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authorMarion Lafon <mar.lafon.ml@gmail.com>2018-05-14 16:28:59 +0200
committerMarion Lafon <mar.lafon.ml@gmail.com>2018-05-24 10:46:38 +0200
commitdcb1d68179c3802daeeef46ef63593f59aee64e9 (patch)
treee15d5da2fdf3b9c3368bcaed355891dbe496b111 /miasm2/arch/arm/ira.py
parent652bf298e56214c33c2291064eba00d1559a07aa (diff)
downloadmiasm-dcb1d68179c3802daeeef46ef63593f59aee64e9.tar.gz
miasm-dcb1d68179c3802daeeef46ef63593f59aee64e9.zip
armtl change branch pc offset
Modify some armtl instr to match with documentation
Diffstat (limited to 'miasm2/arch/arm/ira.py')
-rw-r--r--miasm2/arch/arm/ira.py16
1 files changed, 15 insertions, 1 deletions
diff --git a/miasm2/arch/arm/ira.py b/miasm2/arch/arm/ira.py
index cfcb294c..ed96376b 100644
--- a/miasm2/arch/arm/ira.py
+++ b/miasm2/arch/arm/ira.py
@@ -2,7 +2,8 @@
 
 from miasm2.ir.analysis import ira
 from miasm2.arch.arm.sem import ir_arml, ir_armtl, ir_armb, ir_armtb
-
+from miasm2.expression.expression import ExprAff, ExprOp
+from miasm2.ir.ir import AssignBlock
 
 class ir_a_arml_base(ir_arml, ira):
     def __init__(self, symbol_pool=None):
@@ -21,6 +22,19 @@ class ir_a_arml(ir_a_arml_base):
         ir_a_arml_base.__init__(self, symbol_pool)
         self.ret_reg = self.arch.regs.R0
 
+    def call_effects(self, ad, instr):
+        return [AssignBlock([ExprAff(self.ret_reg, ExprOp('call_func_ret', ad,
+                                                          self.arch.regs.R0,
+                                                          self.arch.regs.R1,
+                                                          self.arch.regs.R2,
+                                                          self.arch.regs.R3,
+                                                          )),
+                             ExprAff(self.sp, ExprOp('call_func_stack',
+                                                     ad, self.sp)),
+                            ],
+                             instr
+                           )]
+
     def get_out_regs(self, _):
         return set([self.ret_reg, self.sp])