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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-03-11 18:45:22 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-04-18 09:54:48 +0200 |
| commit | b5b8c0626e12f779404606362151c3e373aaa673 (patch) | |
| tree | 8adb5c066284e322b0ce151e0bcf09131f1453cd /miasm2/arch/arm/sem.py | |
| parent | 27b9311cf71da7fd5392a614f23c4042081b868c (diff) | |
| download | miasm-b5b8c0626e12f779404606362151c3e373aaa673.tar.gz miasm-b5b8c0626e12f779404606362151c3e373aaa673.zip | |
Arm/t2: Round ld/st pc relative
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/arm/sem.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index 423b3c1f..d4efba84 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -641,6 +641,9 @@ def st_ld_r(ir, instr, a, a2, b, store=False, size=32, s_ext=False, z_ext=False) else: ad = base + off + # PC base lookup uses PC 4 byte alignemnt + ad = ad.replace_expr({PC: PC & ExprInt(0xFFFFFFFC, 32)}) + dmem = False if size in [8, 16]: if store: |