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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-02-15 08:20:45 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-03-13 14:13:13 +0100 |
| commit | 287cb1bb182112ad8b476a9631f0099163041fdc (patch) | |
| tree | 3913ea7584338a268ffbea1f8a8d2658b44855dc /miasm2/arch/arm/sem.py | |
| parent | c3940991f2461278fdb3c7faff8b270320585556 (diff) | |
| download | miasm-287cb1bb182112ad8b476a9631f0099163041fdc.tar.gz miasm-287cb1bb182112ad8b476a9631f0099163041fdc.zip | |
All: rename vars bloc -> block
Diffstat (limited to 'miasm2/arch/arm/sem.py')
| -rw-r--r-- | miasm2/arch/arm/sem.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index 0ec02907..8c74aa76 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -1252,8 +1252,8 @@ class ir_arml(IntermediateRepresentation): x = ExprAff(x.dst, x.src.replace_expr( {self.pc: ExprInt32(instr.offset + 8)})) instr_ir[i] = x - for b in extra_ir: - for irs in b.irs: + for irblock in extra_ir: + for irs in irblock.irs: for i, x in enumerate(irs): x = ExprAff(x.dst, x.src.replace_expr( {self.pc: ExprInt32(instr.offset + 8)})) |