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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-10-11 19:35:18 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-10-12 16:27:58 +0200 |
| commit | 329f058141844a2e499140d61887324c824a2d5e (patch) | |
| tree | 66261d99f914eec532d26c20aadf6817fd196b10 /miasm2/arch/mep/jit.py | |
| parent | 58bb989db435fff2ee63d121ece8c66eedbce8dc (diff) | |
| download | miasm-329f058141844a2e499140d61887324c824a2d5e.tar.gz miasm-329f058141844a2e499140d61887324c824a2d5e.zip | |
All: updt api
Diffstat (limited to '')
| -rw-r--r-- | miasm2/arch/mep/jit.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/miasm2/arch/mep/jit.py b/miasm2/arch/mep/jit.py index 33eb5c3c..913d508f 100644 --- a/miasm2/arch/mep/jit.py +++ b/miasm2/arch/mep/jit.py @@ -91,14 +91,14 @@ class jitter_mepl(Jitter): def pop_uint16_t(self): regs = self.cpu.get_gpreg() - x = upck16(self.vm.get_mem(regs["SP"], 2)) + x = self.vm.get_u16(regs["SP"]) regs["SP"] += 2 self.cpu.set_gpreg(regs) return x def get_stack_arg(self, n): regs = self.cpu.get_gpreg() - x = upck16(self.vm.get_mem(regs["SP"] + 2 * n, 2)) + x = self.vm.get_u16(regs["SP"] + 2 * n) return x def init_run(self, *args, **kwargs): |