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| author | Camille Mougey <commial@gmail.com> | 2018-08-29 16:27:06 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-29 16:27:06 +0200 |
| commit | 7c0d412120abbcfaa51fdb1dd231a27595c873ed (patch) | |
| tree | 43226fee7292a9a4912ea1d3d0d9728d2aefbcfd /miasm2/arch/mep/sem.py | |
| parent | 86e458d488b02bf3479f9c5a42bb56de23c3ea80 (diff) | |
| parent | 253547e35343aed844e7bcb033c610409fcbd21e (diff) | |
| download | miasm-7c0d412120abbcfaa51fdb1dd231a27595c873ed.tar.gz miasm-7c0d412120abbcfaa51fdb1dd231a27595c873ed.zip | |
Merge pull request #828 from serpilliere/fix_lgtm_1
Code cleaning: lgtm.com
Diffstat (limited to 'miasm2/arch/mep/sem.py')
| -rw-r--r-- | miasm2/arch/mep/sem.py | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/miasm2/arch/mep/sem.py b/miasm2/arch/mep/sem.py index 3558de70..e1d4c5fa 100644 --- a/miasm2/arch/mep/sem.py +++ b/miasm2/arch/mep/sem.py @@ -505,8 +505,8 @@ def bnez(reg_test, disp8): """BNEZ - Branch if the register does not store zero.""" # if(Rn!=0) PC <- PC + SignExt((disp8)7..1||0) - dst = disp8 if "-"(reg_test, i32(0)) else ExprLoc(ir.get_next_break_loc_key(instr), 32) - take_jmp = ExprInt(1, 32) if "-"(reg_test, i32(0)) else ExprInt(0, 32) + dst = disp8 if reg_test else ExprLoc(ir.get_next_break_loc_key(instr), 32) + take_jmp = ExprInt(1, 32) if reg_test else ExprInt(0, 32) PC = dst ir.IRDst = dst @@ -516,8 +516,8 @@ def beqi(reg_test, imm4, disp16): """BEQI - Branch if the register stores imm4.""" # if(Rn==ZeroExt(imm4)) PC <- PC +SignExt((disp17)16..1||0) - dst = ExprLoc(ir.get_next_break_loc_key(instr), 32) if "-"(reg_test, imm4) else disp16 - take_jmp = ExprInt(0, 32) if "-"(reg_test, imm4) else ExprInt(1, 32) + dst = ExprLoc(ir.get_next_break_loc_key(instr), 32) if (reg_test - imm4) else disp16 + take_jmp = ExprInt(0, 32) if (reg_test - imm4) else ExprInt(1, 32) PC = dst ir.IRDst = dst @@ -527,8 +527,8 @@ def bnei(reg_test, imm4, disp16): """BNEI - Branch if the register does not store imm4.""" # if(Rn!=ZeroExt(imm4)) PC <- PC+SignExt((disp17)16..1||0) - dst = disp16 if "-"(reg_test, imm4) else ExprLoc(ir.get_next_break_loc_key(instr), 32) - take_jmp = ExprInt(1, 32) if "-"(reg_test, imm4) else ExprInt(0, 32) + dst = disp16 if (reg_test - imm4) else ExprLoc(ir.get_next_break_loc_key(instr), 32) + take_jmp = ExprInt(1, 32) if (reg_test - imm4) else ExprInt(0, 32) PC = dst ir.IRDst = dst @@ -560,8 +560,8 @@ def beq(rn, rm, disp16): """BEQ - Branch if the two registers are equal.""" # if(Rn==Rm) PC <- PC +SignExt((disp17)16..1||0) - dst = ExprLoc(ir.get_next_break_loc_key(instr), 32) if "-"(rn, rm) else disp16 - take_jmp = ExprInt(0, 32) if "-"(rn, rm) else ExprInt(1, 32) + dst = ExprLoc(ir.get_next_break_loc_key(instr), 32) if (rn - rm) else disp16 + take_jmp = ExprInt(0, 32) if (rn - rm) else ExprInt(1, 32) PC = dst ir.IRDst = dst @@ -571,8 +571,8 @@ def bne(rn, rm, disp16): """BNE - Branch if the two registers are not equal.""" # if(Rn!=Rm) PC <- PC +SignExt((disp17)16..1||0) - dst = disp16 if "-"(rn, rm) else ExprLoc(ir.get_next_break_loc_key(instr), 32) - take_jmp = ExprInt(1, 32) if "-"(rn, rm) else ExprInt(0, 32) + dst = disp16 if (rn - rm) else ExprLoc(ir.get_next_break_loc_key(instr), 32) + take_jmp = ExprInt(1, 32) if (rn - rm) else ExprInt(0, 32) PC = dst ir.IRDst = dst |