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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-08 17:02:35 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-02-09 10:55:39 +0100 |
| commit | eca476334f93f023e57048453eb9ec4ee4fab9d2 (patch) | |
| tree | 08ea36af5f8f7f27222631cdbf0b9f18aa3248cc /miasm2/arch/mips32/ira.py | |
| parent | 47811fe5a56c8071ab5064e1f84ca64389941eec (diff) | |
| download | miasm-eca476334f93f023e57048453eb9ec4ee4fab9d2.tar.gz miasm-eca476334f93f023e57048453eb9ec4ee4fab9d2.zip | |
IRBlock: replace irs by assignblks
Diffstat (limited to 'miasm2/arch/mips32/ira.py')
| -rw-r--r-- | miasm2/arch/mips32/ira.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py index f1e21a41..ab242815 100644 --- a/miasm2/arch/mips32/ira.py +++ b/miasm2/arch/mips32/ira.py @@ -21,7 +21,7 @@ class ir_a_mips32l(ir_mips32l, ira): for irb in ir_blocks: pc_val = None lr_val = None - for assignblk in irb.irs: + for assignblk in irb.assignblks: pc_val = assignblk.get(self.arch.regs.PC, pc_val) lr_val = assignblk.get(self.arch.regs.RA, lr_val) |