Arch/jit: add endianess support jitters

1 files changed, 12 insertions, 4 deletions

diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py
index 61fa8a5a..93223896 100644
--- a/miasm2/arch/mips32/jit.py
+++ b/miasm2/arch/mips32/jit.py
@@ -1,7 +1,7 @@
 from miasm2.jitter.jitload import jitter
 from miasm2.core import asmbloc
 from miasm2.core.utils import *
-from miasm2.arch.mips32.sem import ir_mips32
+from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b
 
 import logging
 
@@ -11,13 +11,13 @@ hnd.setFormatter(logging.Formatter("[%(levelname)s]: %(message)s"))
 log.addHandler(hnd)
 log.setLevel(logging.CRITICAL)
 
-class jitter_mips32(jitter):
+class jitter_mips32l(jitter):
 
     def __init__(self, *args, **kwargs):
         sp = asmbloc.asm_symbol_pool()
-        jitter.__init__(self, ir_mips32(sp), *args, **kwargs)
+        jitter.__init__(self, ir_mips32l(sp), *args, **kwargs)
+        self.vm.set_little_endian()
         self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC
-        self.ir_arch.attrib = 'l'
 
     def push_uint32_t(self, v):
         self.cpu.SP -= 4
@@ -35,3 +35,11 @@ class jitter_mips32(jitter):
     def init_run(self, *args, **kwargs):
         jitter.init_run(self, *args, **kwargs)
         self.cpu.PC = self.pc
+
+
+class jitter_mips32b(jitter_mips32l):
+    def __init__(self, *args, **kwargs):
+        sp = asmbloc.asm_symbol_pool()
+        jitter.__init__(self, ir_mips32b(sp), *args, **kwargs)
+        self.vm.set_big_endian()
+        self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC