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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2016-07-30 00:12:33 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2016-08-30 11:08:16 +0200 |
| commit | d441330ab409cfb0a8d3e0ebcfccafef54c32cd0 (patch) | |
| tree | b0dda66bbed78a243b6d32ec8760dd69ec5e367a /miasm2/arch/mips32/jit.py | |
| parent | f2a9a353b32bf59a06b8738ab05e1d20109f71c9 (diff) | |
| download | miasm-d441330ab409cfb0a8d3e0ebcfccafef54c32cd0.tar.gz miasm-d441330ab409cfb0a8d3e0ebcfccafef54c32cd0.zip | |
Jitter: code generator rework
Diffstat (limited to 'miasm2/arch/mips32/jit.py')
| -rw-r--r-- | miasm2/arch/mips32/jit.py | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index 93223896..aca85de5 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -1,9 +1,10 @@ +import logging + from miasm2.jitter.jitload import jitter from miasm2.core import asmbloc from miasm2.core.utils import * from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b - -import logging +from miasm2.jitter.codegen import CGen log = logging.getLogger('jit_mips32') hnd = logging.StreamHandler() @@ -17,7 +18,6 @@ class jitter_mips32l(jitter): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_mips32l(sp), *args, **kwargs) self.vm.set_little_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC def push_uint32_t(self, v): self.cpu.SP -= 4 @@ -42,4 +42,3 @@ class jitter_mips32b(jitter_mips32l): sp = asmbloc.asm_symbol_pool() jitter.__init__(self, ir_mips32b(sp), *args, **kwargs) self.vm.set_big_endian() - self.ir_arch.jit_pc = self.ir_arch.arch.regs.PC |