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| author | Camille Mougey <commial@gmail.com> | 2017-06-06 12:24:31 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-06-06 12:24:31 +0200 |
| commit | 443a811aa92a31d3c2ae89937c5abb497bcc30ff (patch) | |
| tree | 70937e30d5475f1c0b137ffc343e312323c50970 /miasm2/arch/mips32/jit.py | |
| parent | b772f2d9c7aceb7d1ca87cdefd708d4f65d71623 (diff) | |
| parent | ded504718e83ffcc63ef42cc27159ef998ed211b (diff) | |
| download | miasm-443a811aa92a31d3c2ae89937c5abb497bcc30ff.tar.gz miasm-443a811aa92a31d3c2ae89937c5abb497bcc30ff.zip | |
Merge pull request #522 from serpilliere/ir_ro
Ir ro
Diffstat (limited to 'miasm2/arch/mips32/jit.py')
| -rw-r--r-- | miasm2/arch/mips32/jit.py | 31 |
1 files changed, 17 insertions, 14 deletions
diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index 9b46589f..493da595 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -5,7 +5,7 @@ from miasm2.core import asmblock from miasm2.core.utils import pck32, upck32 from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b from miasm2.jitter.codegen import CGen -from miasm2.ir.ir import AssignBlock +from miasm2.ir.ir import AssignBlock, IRBlock import miasm2.expression.expression as m2_expr log = logging.getLogger('jit_mips32') @@ -40,24 +40,27 @@ class mipsCGen(CGen): def block2assignblks(self, block): irblocks_list = super(mipsCGen, self).block2assignblks(block) - for instr, irblocks in zip(block.lines, irblocks_list): - if not instr.breakflow(): - continue - for irblock in irblocks: - for idx, assignblock in enumerate(irblock.irs): + for irblocks in irblocks_list: + for blk_idx, irblock in enumerate(irblocks): + has_breakflow = any(assignblock.instr.breakflow() for assignblock in irblock.irs) + if not has_breakflow: + continue + + irs = [] + for assignblock in irblock.irs: if self.ir_arch.pc not in assignblock: + irs.append(AssignBlock(assignments, assignblock.instr)) continue - new_assignblock = dict(assignblock) + assignments = dict(assignblock) # Add internal branch destination - new_assignblock[self.delay_slot_dst] = assignblock[ + assignments[self.delay_slot_dst] = assignblock[ self.ir_arch.pc] - new_assignblock[self.delay_slot_set] = m2_expr.ExprInt(1, 32) + assignments[self.delay_slot_set] = m2_expr.ExprInt(1, 32) # Replace IRDst with next instruction - new_assignblock[self.ir_arch.IRDst] = m2_expr.ExprId( - self.ir_arch.get_next_instr(instr)) - irblock.dst = m2_expr.ExprId( - self.ir_arch.get_next_instr(instr)) - irblock.irs[idx] = AssignBlock(new_assignblock, assignblock.instr) + assignments[self.ir_arch.IRDst] = m2_expr.ExprId( + self.ir_arch.get_next_instr(assignblock.instr)) + irs.append(AssignBlock(assignments, assignblock.instr)) + irblocks[blk_idx] = IRBlock(irblock.label, irs) return irblocks_list |